Circuit to detect pulse train missing pulses

[cm64]

I have a 4MHz pulse train output of a device with 50% duty cycle. I need a circuit which can turn on a relay if a pulse is missing. I can take care of the relay interfacing but need help with the detection part. I can tweak by using SPICE if I can find a generic topology. Is there a way to achieve this(for 4MHz pulse train) without using an FPGA or a microcontroller?

 

[KlausST]

Hi,

4MHz means 250ns.
50% duty cycle means 125ns ON and 125ns OFF.

My solution:
* Buffer (my be omitted)
* D||R and a C to GND ( buffer discharges capacitor fast. R charges capacitor slowly)
* Schmitt trigger connected at C

Choose R x C in a way that the schmitt trigger gets activated after about 250ns of no LOW.

Please define relay timing and operation mode:
* it should be operated when a (single) pulse is missing. (this takes about 250ns, but for the relay contacts may be delayed by several milliseconds)
* but when and how should the relay release? Manually? after time?

Klaus

 

[cm64]

Hi,

4MHz means 250ns.
50% duty cycle means 125ns ON and 125ns OFF.

My solution:
* Buffer (my be omitted)
* D||R and a C to GND ( buffer discharges capacitor fast. R charges capacitor slowly)
* Schmitt trigger connected at C

Choose R x C in a way that the schmitt trigger gets activated after about 250ns of no LOW.

Please define relay timing and operation mode:
* it should be operated when a (single) pulse is missing. (this takes about 250ns, but for the relay contacts may be delayed by several milliseconds)
* but when and how should the relay release? Manually? after time?

Klaus

Thanks for the answer. At the moment requirements relay part is not known(I guess a few ms is fine). The relay should be released manually.

 

[KlausST]

Hi,

then use an RS flip flop.
SET with schmitt trigger output.
RESET manually.
OUTPUT to relay driver.

Klaus

 

[betwixt]

Alternative methods:
1. monostable triggered by pulses but timed so it flips output state if it doesn't get reset in time.
2. a triggered oscillator with free-running frequency close to 4MHz, output XOR'ed with the input will create a pulse if its output no longer matches the triggering signal.

Brian.

 

[danadakk]

I think this should work. This is a micro with programmable fabric on it,
but you will not be using the CPU and only small amount of the fabric.

Basically it detects if either high or low level of pulse train coming in fails
to meet 125 nS width (4 Mhz, 1/2 period high or low).

You drag and drop onchip resources from the chip specific resource catalog,
3'rd window from left, onto canvas, wire up internal and external to pins as needed,
hit build button, tool takes care of routing, initialization, and programming.

No code, single chip..

Note right hand window, resources used/left, shows maybe no more than 2% of
resources used, in case you need other logic, capabilities. Lots of analog as well.

The detection sets the "D", you have to activate its reset pin to clear it. You could
put other logic on the "D" reset , like a timer, analog threshold, or value or combinatorial....
whatever. All in chip.....

Timing accuracy over T and V is +/- 2%. If you need more accurate timing hand a xtal off it.

IDE and Compiler free. You need the Compiler because when you hit the build button,
some code is auto generated to setup chip. Normally you do not touch that code, if
not using CPU or the more advanced features of chip. Thats why this is effectively a
codeless design. Small board ~ $15 for design/debug.


Regards, Dana.

 

[d123]

Hi,

Page 11 of beautiful Signetics 555 timer booklet has a really simple missing pulse detector circuit ( a 555 monostable and one PNP). A timer IC that can operate at the required speed (fastest 555 I'm aware of claims 3 MHz) might accomodate the general idea.

 

[crutschow]

Below is the LTspice simulation of a missing pulse circuit that uses a 74HC14 Schmitt-trigger inverter gate package to be fast enough for you requirements.
I turns on the relay if the clock stops either high or low.

When the clock is available (green trace), the output from U1a keeps capacitor C1 (yellow trace) pulled low through D2.
When the clock stops, the output of U1a goes high and C1 starts to charge through R1.
When the voltage reaches the input threshold of U1b it goes low, causing U1c to go high and turning on the transistor and the relay.

 

[danadakk]

You might want to consider some detrimental effects using 74HC14 solutions -

1) V sensitivity of threshold -

2) T sensitivity threshold, not exactly complete.

3) The sim is shown for a loss of many 4 Mhz cycles, but I gather you want circuit
to catch minimum just one cycle drop, is that correct ? In fact you want to know
if either high or low time exceeds 125 nS (you stated input was 50% duty cycle),
on 1 or more cycles, correct ?

4) Overall the timing accuracy of a 74HC14 solution might be fine for Khz kinds
of problems, but Mhz I thing lack of accurate error budget info and added compli-
cations of passive component T and V effects asking for a design that is marginal
at best.

5) Power up/down sequencing of design not known, re causing glitches in relay
operation.


Regards, Dana.

 

[Easy peasy]

There is a standard TLC555 ckt that is a missing pulse detector

 

[D.A.(Tony)Stewart]

The most reliable, simplest,and cheapest solution is the logic retriggerable one shot IC, the 74LVC1G123. $0.15 (1) and comes in DIP and SMD 5ns retriggerable time from 100 pF 2% NPO and 2k 1% to detect a single missing pulse allowing about 10 ns after a 250 ns interval with no expect clock edge.

You may choose a different R value if you wish, with a spec. RC = kT see fig 14 . NPO caps are most accurate. https://www.digikey.ca/en/products/detail/nexperia-usa-inc/74LVC1G123GT-115/3679031

 

[crutschow]

I need a circuit which can turn on a relay if a pulse is missing.

Do you need to detect if just one pulse is missing?

 

[cm64]

Do you need to detect if just one pulse is missing?

I meant the circuit should be able to detect the first missing pulse and activate the relay(latch it forever so system stops).

 

[cm64]

The most reliable, simplest,and cheapest solution is the logic retriggerable one shot IC, the 74LVC1G123. $0.15 (1) and comes in DIP and SMD 5ns retriggerable time from 100 pF 2% NPO and 2k 1% to detect a single missing pulse allowing about 10 ns after a 250 ns interval with no expect clock edge.

You may choose a different R value if you wish, with a spec. RC = kT see fig 14 . NPO caps are most accurate. https://www.digikey.ca/en/products/detail/nexperia-usa-inc/74LVC1G123GT-115/3679031

Can you provide/sketch a circuit how to use this IC for this purpose?

 

[KlausST]

Hi,

Can you provide/sketch a circuit how to use this IC for this purpose?

This is the reason why I always recommend to directly refer to the manufacturer´s internet site:

https://www.ti.com/product/SN74LVC1G123?keyMatch=SN74LVC1G123&tisearch=search-everything&usecase=GPN#tech-docs

TI provides additional information. (NEXPERIA sadly not that much)
See the application note: "Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A)": https://www.ti.com/lit/pdf/slva720

I think it solves all possible questions.

Klaus

 

[danadakk]

I think you will find if you do worst case error budget on timing you will
find this suffers same problems as all 74HC. Passive tolerances, T and V
effects, wide sloppy threshold range, etc, power sequencing causing false
triggers.....

But if this is a one off design go for it, you can put pots in to adjust circuit
by hand.

Page 11 -

https://www.ti.com/lit/an/sdla006a/sdla006a.pdf?ts=1631276011254&ref_url=https%253A%252F%252Fwww.google.com%252F

Regards, Dana.

 

[D.A.(Tony)Stewart]

I think you will find if you do worst case error budget on timing you will
find this suffers same problems as all 74HC. Passive tolerances, T and V
effects, wide sloppy threshold range, etc, power sequencing causing false
triggers.....

But if this is a one off design go for it, you can put pots in to adjust circuit
by hand.

Page 11 -

https://www.ti.com/lit/an/sdla006a/sdla006a.pdf?ts=1631276011254&ref_url=https%253A%252F%252Fwww.google.com%252F

Regards, Dana.

I've not verified this , but there will be correlation except k factor is inversely related to C , k( HC ) reduces with rising f smaller C while k(LVC) rises with reducing C and both sensitivity (slope rise with smaller C). Yet LVC version is <50% of the RdsOn (22~25) HC class (50~66) [nominal] of CMOS at Vdd rated.

However for a missing pulse to operate it only needs to detect anything > 200 ns + 1/frequency error (ppm) , but to detect a slow continuous clock cannot be detected unless you have a spec for this and use a PLL reference. Nor can it detect extra pulses. What is the real purpose? And environment ? And more importantly, (all) the real specs?

 

[crutschow]

I meant the circuit should be able to detect the first missing pulse and activate the relay(latch it forever so system stops).

Will the pulses ever start again after they stop?