CIC filter for sigma-delta converter

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ultralowpower

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sigma delta cic

Hi,

I have one question about the implementation of a CIC decimator filter. How I can meet my especifications of a output range of 16 bits in the CIC filter output? I have a 2nd order sigma-delta modulator that has a bit stream (1 bit output). Can anyone give me some information about this? The best information is a CIC filter RTL (or code) with explicit one bit input and explicit 16 bits output.

Sorry about my english, is not my primary language and thanks for help.

Brito.

PS: (R=256)
 

The concept is:
1. output is 1/(2 power of 15) if the 1 bit input is 1'b1
2. output is -1/(2 power of 15) if the 1 bit input is 1'b0

example of the code:

module test ( filter_in, filter_out );
input filter_in;
output [15:0] filter_out;

assign filter_out = (filter_in == 1'b0) ? 16'hffff : 16'h0001;
endmodule

Please click "Helped" if i did help. Thanks.
 

The number of output bits in sigma-delta converter depends upon the bandwidth and the sampling rate, higher the oversampling ratio (Sampling Rate/bandwidth) the more bits (wordlength) you may achieve.
 

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