No, he suggests a reduction of register width that follows a defined error criterion defined in equation (21). U.-Meyer-Baese has a chapter in his excellent DSP with FPGA titled Hogenauer Pruning Theory. He supplied a tool to calculate the bit reduction, also other CIC design tools are using Hogenauers algorithm, e. g. Alteras CIC MegaCore. The pruning can be basically calculated in VHDL code.Hogenauer assumed Bmax to be required at any stage
mesfet said:Thanks the prompt reply. I know setting all the integrator and differentiator to Bmax works fine, as proven in simulation. I am trying to figure out what is the reason behind. What trouble me is the fact that Bmax is the required bitwidth at output, but how come bitwidth of the stages in between are also Bmax. Shouldn't they be less than Bmax?
Mesfet
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