Choosing a verification language for RTL codes in VHDL

[adap]

VHDL and SystemVerilog

I am currently writing RTL code in VHDL and I am interested in using one of the verification languages (SystemVerilog, E, Vera, SystemC) for verification.

As far as I know SystemC (NC Sim simulator supports it) can be used for testing both VHDL and Verilog RTL code.

I saw that Modelsim supports SystemVerilog for testing but does the RTL code has to be in Verilog too when the testbench is in SystemVerilog or is the simulator able to support mixed language?

What about the Specman E and the Synopsys tool for Vera?
Do you know which simulators cooperate with these tools?

And what about PSL? Is it something independent?

If someone has used any of the verification languages I would really like to hear from you.
Thanks.

 

[bigyellow]

Re: VHDL and verification languages

co-ask as well

especially about the PSL, what are the advanced properties of PSL compared to other verification languages?

How is the performance of SystemC in verification?

 

[adap]

VHDL and SystemVerilog

Has somebody worked with these verification languages and with PSL?

 

[stevepre]

Re: VHDL and SystemVerilog

PSL is the "assertion" language. You still need verilog/vhdl/... whatever testbench to test your design, while the PSL can give you more visibility to the internal of the design.

PSL can also be used as a "static" verification tool (verifying property without running simulation). However, it's not so easy to write a good PSL for this purpose and there are not many tools focused on this because of the usability and designer's acceptance.