alzomor
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Hi
I am using ISE 7.1i for Virtex4 .
MY Target FPGA is on ARM926EJ-s Versatile Board.
ARM9 is debugged using RVDS SW By USB Jtag connector on the board which communicate to the host PC through USB and translates USB command to JTAG Domain on my board.
I am using Chipscope7.1i evaluation version for testing some signals.
But Each time I get the message "INF: Found 0 Core Units in the Jtag Device Chain"
and I have checked the answer record #19337
I am not sure if I am configuring the ICON correctly
My Questions is How to configure this options in ICON core generator
* Disabling the boundry scan Component Instance
* Selecting the Boundy scan chain
* Including Boundry scan ports
* Disabling Jtag Clock BUFG Insertion
May you suggest me how to configure this options PLS.
Salam
Hossam Alzomor
www(.)i-g(.)org
I am using ISE 7.1i for Virtex4 .
MY Target FPGA is on ARM926EJ-s Versatile Board.
ARM9 is debugged using RVDS SW By USB Jtag connector on the board which communicate to the host PC through USB and translates USB command to JTAG Domain on my board.
I am using Chipscope7.1i evaluation version for testing some signals.
But Each time I get the message "INF: Found 0 Core Units in the Jtag Device Chain"
and I have checked the answer record #19337
I am not sure if I am configuring the ICON correctly
My Questions is How to configure this options in ICON core generator
* Disabling the boundry scan Component Instance
* Selecting the Boundy scan chain
* Including Boundry scan ports
* Disabling Jtag Clock BUFG Insertion
May you suggest me how to configure this options PLS.
Salam
Hossam Alzomor
www(.)i-g(.)org