grubby23
Junior Member level 3
Hi
I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a Instruction width of 6 bits. I have a design for which I had automatically generated a JTAG Controller. I can successfully sythesize the design as well as the JTAG TAP. The problem is just that when I use ChipScope Pro with to connect to the device it tells me that there are 0
Core units found in the JTAG device chain.
I have the following options when generating the JTAG TAP Controller:
Instruction Register Bid Width: 6 (this is what Chipscope pro tells me)
Version Number: 0
Pert Number: 0
Manufacturer: 0
TDI Signal name: tdi
TDO Signal name: tdo
TMS Signal name: tms
TCK Signal name: tck
TRST Signal name: trst_n
I dont think that Version number, Part Number and Manufacturer are critical, right? Anyone an idea what I could have been missing?
Probably something obvious when running the synthesis with Xilinx XST?
Many thanks for helpful tips!
I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a Instruction width of 6 bits. I have a design for which I had automatically generated a JTAG Controller. I can successfully sythesize the design as well as the JTAG TAP. The problem is just that when I use ChipScope Pro with to connect to the device it tells me that there are 0
Core units found in the JTAG device chain.
I have the following options when generating the JTAG TAP Controller:
Instruction Register Bid Width: 6 (this is what Chipscope pro tells me)
Version Number: 0
Pert Number: 0
Manufacturer: 0
TDI Signal name: tdi
TDO Signal name: tdo
TMS Signal name: tms
TCK Signal name: tck
TRST Signal name: trst_n
I dont think that Version number, Part Number and Manufacturer are critical, right? Anyone an idea what I could have been missing?
Probably something obvious when running the synthesis with Xilinx XST?
Many thanks for helpful tips!
