ChipScope 21 Base Types in my MGT design !

[kaiserschmarren87]

ChipScope core inserter has 21 Base Types in my MGT design !

Hello,

I am working on MGT Virtex-4 with a design in it. The design is pretty huge with hundreds of internal signals. Now I am trying to debug the design using ChipScope.
I created *.cdc file and when I get into core inserter to capture the parameters of my design, the 'NetName' and the 'Source Instance' have quite different name (I guess while Synthesis the name gets changed) but I am worried about the "Base Types" to choose since it has 21 different base types as below;
"GT11, LUT1, LUT2, LUT3, LUT4, MUXCY, INV, LUT4_L, LUT3_D, LUT4_D, FDE, FDCE, FD, FDC, FDP, MUXF5, RAMB16, XORCY, SRL16E, LUT2_D, MUXF6."

The design has many state machines, registers etc. My question is, which Base Type is important and which one can be ignored ? I am asking this because for some signals which I select, ChipScope fails to show OUTPUT. Since my main target is debugging the design, it would be great to know about ChipScope.


And also, has anyone used FPGAXpose from Sandbyte ? (It is also a debugging tool used along with Xilinx ISE and ChipScope Pro).
**broken link removed**

Thank you.

 

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The only reliable types are the flip-flops I.e. the fdxx ones. Unless you add the correct keep/preserve attributes to wire signals, the lut ones are unreliable when looking at the name.

 

[kaiserschmarren87]

The only reliable types are the flip-flops I.e. the fdxx ones. Unless you add the correct keep/preserve attributes to wire signals, the lut ones are unreliable when looking at the name.

Suppose I want to debug some signal which are not under fdxx base types, then how to get them into ChipScope ?
Will Vivado ILA help at this point ? Or is there any debugging tool which might come in handy ?

 

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Use keep/preserve attributes in your code to make sure the signals exist after synthesis.

for verilog that would be something like:

(* KEEP = "TRUE" *) wire  some_ila_signal;

something like that should work on either ISE or Vivado and will keep the signal some_ila_signal in the design even if it feeds a flip-flop, basically what you end up with is a LUT that generates some_ila_signal that doesn't use any direct connection to the flip-flop in the same slice, so doing this could make your Fmax suffer.

Regards

 

[kaiserschmarren87]

Use keep/preserve attributes in your code to make sure the signals exist after synthesis.

for verilog that would be something like:

(* KEEP = "TRUE" *) wire  some_ila_signal;

something like that should work on either ISE or Vivado and will keep the signal some_ila_signal in the design even if it feeds a flip-flop, basically what you end up with is a LUT that generates some_ila_signal that doesn't use any direct connection to the flip-flop in the same slice, so doing this could make your Fmax suffer.

Regards

I will check with fdxx for now since I need to look at keep/preserve attribute before doing it.

I came across this FPGAXpose debugging tool from **broken link removed**. Any clue about its help with ChipScope ?

 

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Looks interesting if it can do what it claims. Never used it before.

 

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Actually took a better look at the datasheet.

It's not like chipscope in that it isn't a logic analyzer. It looks like it allows capturing a snapshot of the design register contents, which would limit it's usefulness. Not entirely sure how it can be triggered real time with an internal condition, especially as it claims to need no logic resources.

 

[kaiserschmarren87]

Actually took a better look at the datasheet.

It's not like chipscope in that it isn't a logic analyzer. It looks like it allows capturing a snapshot of the design register contents, which would limit it's usefulness. Not entirely sure how it can be triggered real time with an internal condition, especially as it claims to need no logic resources.

Yeah I have checked the manual and video tutorial. I agree with what you said. It is used along with ChipScope Pro to analyse the register contents. Apart from it I do not see any other use. I have not yet used it but happened to find it.