#### jyothikiranmai

##### Newbie level 1

this prog is to calculate the gain of the each vertices. the gain is the addition of weights(wt) in "initial_trail" prog. addition is done in "adder24" prog. the top module is "gain_cal".

library ieee;

use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

package FM is type int_vect is array (NATURAL RANGE<>) OF STD_LOGIC_VECTOR(3 downto 0);

type int_vect1 is array (NATURAL RANGE<>) OF STD_LOGIC_VECTOR(4 downto 0);

function conv1(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;

end package FM;

package body FM is

function conv1(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is

variable result: STD_LOGIC_VECTOR ((SIZE-1) downto 0);

variable temp: integer;

begin

temp := ARG;

for i in 0 to SIZE-1 loop

if (temp mod 2) = 1 then

result(i) := '1';

else

result(i) := '0';

end if;

temp := temp / 2;

end loop;

return result;

end conv1;

end package body FM;

---------GAIN_CAL-------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

use work.FM.all;

entity gain_cal is

port(ver : in STD_LOGIC_VECTOR(2 downto 0) ;

gain: out std_logic_vector(3 downto 0));

end;

architecture beh of gain_cal is

component initial_trail

port(current_ver : in STD_LOGIC_VECTOR(2 downto 0);

next_ver: in integer;

wt: out STD_LOGIC_VECTOR(3 downto 0));

end component;

component adder24

port (

A : in STD_LOGIC_VECTOR(3 downto 0);

B : in STD_LOGIC_VECTOR(3 downto 0);

OUTPUT : out STD_LOGIC_VECTOR(4 downto 0)

);

end component ;

-- signal nv : STD_LOGIC_VECTOR(2 downto 0);

signal w: int_vect(0 to 7);

signal g: int_vect1(1 to 6);

begin

label1: for i in integer range 1 to 6 generate

begin

w(0)<="0000";

-- nv<=conv1(i,3);

u1: initial_trail port map(ver,i,w(i));

u2:adder24 port map (w(i-1),w(i),g(i));

w(i+1)<=g(i)(3 downto 0 );

end generate label1;

gain<=w(7);

end beh;

--------------------------------------------------------

--ADDER24----

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

entity adder24 is

port (

A : in STD_LOGIC_VECTOR(3 downto 0);

B : in STD_LOGIC_VECTOR(3 downto 0);

OUTPUT : out STD_LOGIC_VECTOR(4 downto 0)

);

end adder24;

architecture Behavioral of adder24 is

signal A_INT : SIGNED (4 downto 0);

signal B_INT : SIGNED (4 downto 0);

signal OUTPUT_VAR : SIGNED (4 downto 0);

begin

A_INT <=SIGNED(A(3) & A);

B_INT <=SIGNED(B(3) & B);

OUTPUT_VAR <= A_INT + B_INT;

OUTPUT <= STD_LOGIC_VECTOR(OUTPUT_VAR);

end Behavioral;

---------------------------------------------------

---INITIAL_TRAIL--

library ieee;

use ieee.std_logic_1164.all;

use work.FM.all;

entity initial_trail is

port(current_ver : in STD_LOGIC_VECTOR(2 downto 0);

next_ver: in integer;

wt: out STD_LOGIC_VECTOR(3 downto 0));

end;

architecture beh of initial_trail is

begin

wt<="1111" when current_ver="001" and next_ver=2 else

"0001" when current_ver="001" and next_ver=3 else

"1111" when current_ver="010" and next_ver=1 else

"0001" when current_ver="010" and next_ver=3 else

"0001" when current_ver="011" and next_ver=1 else

"0001" when current_ver="011" and next_ver=2 else

"1111" when current_ver="011" and next_ver=4 else

"1111" when current_ver="100" and next_ver=5 else

"0001" when current_ver="100" and next_ver=6 else

"1111" when current_ver="101" and next_ver=4 else

"0001" when current_ver="110" and next_ver=4 else

"0000";

end beh;

plz reply me -- immediately.

thnxs

jyothi.