Try loading the CLK1 and CLK2 with the equivalent input capacitance of the charge pump and simulate it again to check the driveability of your inverter I5 and I6. Compare the waveform with and without load.
maybe the inverter can't properly drive the capacitances at high frequencies?
The maximum frequency your logic gates(ex. inverter) can handle depends on their driveability which is their ability to source (charge) or sink (discharge) the capacitive load. I*t=C*V where I is the source /sink current, t is the time to reach the voltage V from 0v, and C is the capacitive load. For higher frequency of operation, assuming the C and V is constant, you need to increase the I(current). To do that, you may want to increase the sizes of your transistors. Maybe in your library you can find inv1, inv2,inv4 etc...they have the same function but their driveability is different. Inverters in parallel can drive higher capacitances, but beware of the input capacitance as this will also increase, if that is the case, you may also want to increase the drive of the gates before the inverter.
Thanks str3,
I think this might be the clue of the whole design.
I have inverter cells like inv8 (W/L=30u/0.7u). Can I use higher driving capabilities? for ex. 60u/0.7u or 100u/0.7u? what are the drawbacks for using high W/L?
should I use high W/L also for NAND gates?
you can use higher W/L ratios to better drive the capacitances. the capacitance value of 100 pF is quite high, so it is possible that u may want to use ur custom inverter, instead of cells from the library, properly sizing the ratios (make some calculations about current and charging time to see the frequency).
however, using high W/L in such applications requires that the previous inverter in your non-overlapping generation chain can effectively drive the output inverter transistor gate. In fact, Cin of your inv. will be tied to the CGS of the mos (approximately 2/3*W*L). So, if you work with the minimum L, increasing W will increase the gate area, making more difficult to drive it. However, the Cin of your inverter will be decisively smaller and easier to drive than the 100 pF load, for very big widths. Maybe you can think to add some kind of buffer between clocks line and charge pump, to help the driving.
Another idea is to realize a chain of inverters with progressively increasing widths to avoid the driving problems. But i think this is not the case, i don't think you need a very very high frequency.
later i'll edit this post
Thanks Braski, your analysis is neat and clear.
I agree with you regarding the Cgs because if I use 100u/0.7 I will have less than 1pF additional capacitance
So what kind of buffer do you suggest? I mean does it need a digital buffer or a sort of source follower?
I haven't designed a digital buffer before. could you please give me some guidance of specs and design topologies?
regarding progressive W/L inverters, which one should have the largest W/L? is it clock input side or load side?
based on what you wrote - ideal sources - works fine - ideal source gives you infinite drive - therefore the pumps charges correctly.
If you have such a small drivers - you can just take that inverter and load it with cap to gnd. You can see the edge degradation when you increade the load.
I would go first for inverter 100./07 and lets see
Thanks Teddy
I think I am fighting against physics now. To drive 100pF load with 100MHz or 200MHz clock I need an infinite transistor width.
It seems that very large W/L=900u/0.7u is capable to drive 50MHz and 100pF or slightly more.
Is there any way to generate non-overlapping clocks driving such high capacitive loads?
browse the literature, but i think 100 pF to drive at 200 Mhz is very very hard. can't u use smaller loads?
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