charge pump design - please help

[processor_ds]

charge pump design

i want to design a charge pump for a pll i want to know how to determine the value of current sources
the phase detector constant = I/(2*pi)
is the value of current source is this I

plz help
thnx

 

[xshou]

You might model PLL in the way for a digial PD:
PD+ChargePump Gain = I/2PI

It's a state average modeling method, which involves use the pulse width to esimate the average signal amplitude as practised by power electronics. Assume high frequency components will be filled out---as in this case by the load cap of the charge pump.

Quantitively, you can do this as long as your PLL BW is below 1/5 of carrier freq according to F. Garner.

For high BW above 1/5, you need go into discrete time modeling to do simulation. The best paper of Z domain model I found is one published over 10 years ago by one IEEE life fellow from UC-Irvine. And for recently results, check out the papers by Michael Perrott from MIT.

 

[processor_ds]

thank u for ur help
the bw of the pll i design is 1/10 the reffernce frequency
fref =80MHz and the loop band width about 8MHz
thank u for papers about z domain analysis

 

[Rayengine]

For charge pump current, In market, many ICs using 5mA or 10mA. New ICs has embedded with new registers which can select the charge punp current to design for different loop time.

 

[rfsystem]

If your BW is only 1/10 of the reference please model your phase margin with the natural delay of the divider. Please keep in mind that the divider makes exact 1 reference delay clock before any frequency change on the vco appears at the phase detector. That could be siginificant at 1/10.

 

[processor_ds]

about the IC's in market i donot use them cause i design a integrated frequency synthiszer , so i want to know how to estimate the chagre pump current to begin to design the loop filter

 

[sunjimmy]

Hi,

Does anyone know how to model the reference clk source with jitter noise based on real crystal?

Since the loop BW design of PLL depends on the noise characteristics from VCO & input reference. To optimize the loop design to achieve low jitter PLL, some real number about input reference jitter, phase noise, rms jitter ... etc is necessary.

Any comment/suggestion is welcome.

Thank you

sunjimmy

 

[rfsystem]

Hi Processor_ds,

if you have to built an integrated PLL there is the following suggestion:

1. Estimate the required phase noise. From your VCO gain you can calculate the equivalent voltage noise density at the input of the VCO. That matches to an equivalent noise resistor. If you want to give the passive loop filter about 20% of the totall out of band phase noise contribution the passive loop filter have to have an equivalent noise resistor 1/5 of the VCO. That is your tolerated series resistor of the passive loop filter. If you require a specific bandwidth you can calculate the required charge pump current.

In that way you can fully determine all parameters of the integrate one.

 

[processor_ds]

nice idea about the vco noise and the passive loop filter , i will try it
thanku rfsystem

about the low phase noise pll , wide band pll is good example to how to optimize loop band width to get good phase noise performance , but this require to use high frequency reffernce

 

[rfsystem]

Increasing the BW to reduce the total noise power of the synthesizer is a possible way to go. There is an optimum. That is where the normally flat noise of the multiplied reference intersect the 1/f of the VCO. In the between the PN gets bumpie. From the phase margin standpoint 1/10 is not the dead end. But the reference injection goes up because of the pulse mismatch and if you using sigma delta the dither power increase rapid with frequency.

So in reality you get much more variables. Try using exel with your own calculations to manage all decisions.

 

[cirand]

Re: charge pump design

Hi, rfsystem
You have said " the divider makes exact 1 reference delay clock before any frequency change on the vco appears at the phase detector. That could be siginificant at 1/10."
how can we analyse this phenomenon in PLL loop transform function?

 

[honey]

Increasing the BW to reduce the total noise power of the synthesizer is a possible way to go. There is an optimum. That is where the normally flat noise of the multiplied reference intersect the 1/f of the VCO. In the between the PN gets bumpie. From the phase margin standpoint 1/10 is not the dead end. But the reference injection goes up because of the pulse mismatch and if you using sigma delta the dither power increase rapid with frequency.

give the relation of these parameters