[SOLVED] change width pulse when simulate problem

Code Verilog - [expand]
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// VerilogA for baitap, ngovaox1, veriloga
`include "constants.vams"
`include "disciplines.vams"
 
module ngovaox1(plus2,minus);
output plus2, minus;
electrical plus2, minus;
 
parameter real period =300m;
parameter real vdd=1;
parameter real d=1u;
 
 
real value2;
analog
begin
/// tao cho data 2
@(timer (0, 8*period))
begin
value2=0;
$discontinuity (1);
end
@(timer (0.000000001, 8*period))
begin
value2=-1;
$discontinuity (1);
end
@(timer (0*period+d, 8*period))
begin
value2=0;
$discontinuity (1);
end
@(timer (1*period, 8*period))
begin
value2=1;
$discontinuity (1);
end
@(timer (1*period+d, 8*period))
begin
value2=0;
$discontinuity (1);
end
@(timer (2*period, 8*period))
begin
value2=1;
$discontinuity (1);
end
@(timer (2*period+d, 8*period))
begin
value2=0;
$discontinuity (1);
end
@(timer (3*period, 8*period))
begin
value2=-1;
$discontinuity (1);
end
@(timer (3*period+d, 8*period))
begin
value2=0;
$discontinuity (1);
end
@(timer (4*period, 8*period))
begin
value2=1;
$discontinuity (1);
end
@(timer (4*period+d, 8*period))
begin
value2=0;
$discontinuity (1);
end
@(timer (5*period, 8*period))
begin
value2=-1;
$discontinuity (1);
end
@(timer (5*period+d, 8*period))
begin
value2=0;
$discontinuity (1);
end
@(timer (6*period, 8*period))
begin
value2=-1;
$discontinuity (1);
end
@(timer (6*period+d, 8*period))
begin
value2=0;
$discontinuity (1);
end
@(timer (7*period, 8*period))
begin
value2=1;
$discontinuity (1);
end
@(timer (7*period+d, 8*period))
begin
value2=0;
$discontinuity (1);
end
 
V(plus2,minus) <+ transition (value2, 0, 0.000001n, 0.000001n);
end
endmodule