change input condition after checking the output voltage in Hspice

[apolama]

Is there any way to change input condition after checking the output value run-time in Hspice?

Actually I need to verify digital operation which needs long time as whole digital circuit needs to be designed first.

If there is any option in Hspice that it can check the output run-time and change the input signal, it can reduce time to check the digitally assisted analog block operation.

thanks in advance.

 

[erikl]

Perhaps you can work with the independent parameters 'time' and/or 'tstop' ?
'time' is the current simulator time, 'tstop' the 'tstop' time of the (last) .TRAN statement.

 

[apolama]

Actually suppose my simulation time is 1us. at 0.5us if the output is greater than vdd/2 i want to change the input condition, may be frequency or amplitude of the input signal.

 

[erikl]

Try the {if endif} construct, something like

.if ( (time >= 0.5e-06) && (Vout > vdd/2) ) Vin = ...
.endif

See the foll. clipping from the HSPICE User Guide: View attachment HSPICE_if_else.pdf

 

[apolama]

I think the if condition cant resolve the output value only the parameter you defined
it is one alternative of .alter command.

i got error "unresolved condition in .if" for .if((time>1e-6))

 

[erikl]

I think the if condition cant resolve the output value only the parameter you defined
it is one alternative of .alter command.

i got error "unresolved condition in .if" for .if((time>1e-6))

May be you are right. But did you also try the evaluation version of a parameter - using 'param' ? I.e

.if ( ('time' >= 0.5e-06) && (Vout > 'vdd/2') ) Vin = ...

... like in this example:
* This measure finds the transition if it exists
.MEASURE Tran MaxVout Max v(D_Output) Goal = ‘v(Vdd)’
* This measure calculates the setup time value
.MEASURE Tran SetupTimeTrig v(Data)Val = ‘v(Vdd)/2’

 

[apolama]

I tried but same result i as got before.
anyway thanks a lot.

i think should consider verilog for this.