Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cells that violates max capacitance constraints

Status
Not open for further replies.

siy010

Newbie level 1
Joined
Feb 20, 2017
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
13
Hi,

I am a graduate student who is new to Prime Time tcl coding. I would like to know if there is a way to know the cells that violate maximum capacitance constraint, such that I can swap cells manually.

Much appreciated.
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,181
Helped
382
Reputation
764
Reaction score
396
Trophy points
83
Activity points
11,148
Swapping a cell won't help, as it is probably the load that is too high. You need timing optimisation to work on the path and fix it.
 

oratie

Full Member level 6
Joined
Jan 10, 2007
Messages
348
Helped
176
Reputation
350
Reaction score
170
Trophy points
1,323
Activity points
3,702
report_constraint -max_capacitance -all_violators

In order to fix just use the higher drive cells.
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,181
Helped
382
Reputation
764
Reaction score
396
Trophy points
83
Activity points
11,148
report_constraint -max_capacitance -all_violators

In order to fix just use the higher drive cells.

No and no.

Max cap can be set as the same value for all cells in a library. Replacing one cell will not fix, as the replacement will likely still violate the same rule. The OP needs timing optimisation to work on the path and fix it with cloning or something similar.

Replacing cells manually is a bad idea, it is not feasible for even small circuits.
 

oratie

Full Member level 6
Joined
Jan 10, 2007
Messages
348
Helped
176
Reputation
350
Reaction score
170
Trophy points
1,323
Activity points
3,702
You are wrong. Max transition is the same value for all drives of all cells in the library. While max_cap is the same only for cells with the same drive strength. Just look inside synopsys .lib file.

It is obviuos: you need to keep reasonable max_tran across all paths of your design for particular working frequency. But the wire length may vary. How to provide the same max_tran for different length wires? Use the cells with different strength. They will provide the same max_tran for different capacitance.
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,181
Helped
382
Reputation
764
Reaction score
396
Trophy points
83
Activity points
11,148
Like I said, max cap CAN be set as the same value for all cells in a library. I have a 16nm library right in front of me that is like that. max_cap is nothing but the highest number in the .lib characterisation tables, the upper limit. You assume all libraries are characterised with dynamic max_cap depending on driving strength. That is not always the case.
 

oratie

Full Member level 6
Joined
Jan 10, 2007
Messages
348
Helped
176
Reputation
350
Reaction score
170
Trophy points
1,323
Activity points
3,702
Ok. Suppose we have a long wire. If we want to satisfy max_tran on it: what we can do?

If we have library with dynamic max_cap for different drives we can use both methods: use high_drive buffer OR use several low_drive buffers.

If we have library with the same max_cap on all cells: the only method available is to use several buffers.

So, whic library gives us more flexibility in terms of area, power, timing?
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,181
Helped
382
Reputation
764
Reaction score
396
Trophy points
83
Activity points
11,148
Ok. Suppose we have a long wire. If we want to satisfy max_tran on it: what we can do?

If we have library with dynamic max_cap for different drives we can use both methods: use high_drive buffer OR use several low_drive buffers.

If we have library with the same max_cap on all cells: the only method available is to use several buffers.

So, whic library gives us more flexibility in terms of area, power, timing?

A naive person would answer the dynamic one. The right question to ask is which library was characterised in a more useful way.

Don't forget max_cap is just a characterisation artefact.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top