@oratie: I've found the cell name *SYN* in the library which is a scan FF with the name "SDFSYNSND2...". I wonder why the normal DFF (w/o scan) has no synchronizing cell type.
Do you know how many clock cycle does it take to transfer the input data to the output? (one or two clock cycles?).
I do not know, why TSMC did not provide non-scan version. Logically this *SYN* flop is equivalent to the normal scan-flop. Just transitor size/ratio was modified to provide better metastability immunity.
The purpose of a 2 FF synchronizer is to get a stable copy of an asynchronous single bit input signal. It does not transfer data (e.g. multi-bit entities or bit streams) consistently between clock domains.
In synchronous logic, each FF delays an input signal by one clock cycle. So does the 2 FF synchronizer.