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it's not about the simulator support, it's about how the gate is described in verilog. check the .v file that came with your std cell library, it might account for metastability in very funky ways or none at all. in my experience, most models just trigger a warning to the user but don't actually do anything.
My .v model didn't account for metastability. I had to find manually turn off timing checks of my synchronizer. Now I know CDC check need to be done by using third-party tool (I used spyglass for this purpose). Thank you for your explanation.