Jun 22, 2008 #1 P pwq1999 Member level 2 Joined Mar 2, 2008 Messages 42 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,578 verilog case i wonder if the case statement without the parallel directive,is it synthesized to a priority case? and if a full case directive, is it also synthesized to a priority case? is there a way to make the synthesizer to synthesize the code into parallel case without any directive in the verilog code ? thanks in advance!
verilog case i wonder if the case statement without the parallel directive,is it synthesized to a priority case? and if a full case directive, is it also synthesized to a priority case? is there a way to make the synthesizer to synthesize the code into parallel case without any directive in the verilog code ? thanks in advance!
Jun 26, 2008 #2 S soloktanjung Full Member level 6 Joined Nov 20, 2006 Messages 364 Helped 51 Reputation 100 Reaction score 43 Trophy points 1,308 Location nowhere Activity points 3,194 verilog case statement Hi, You can find the answer on chapter 3 (p. 84) from the book: Real World FPGA Design with Verilog by Ken Coffman. Thanks.
verilog case statement Hi, You can find the answer on chapter 3 (p. 84) from the book: Real World FPGA Design with Verilog by Ken Coffman. Thanks.
Jun 27, 2008 #3 P pwq1999 Member level 2 Joined Mar 2, 2008 Messages 42 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,578 case in verilog thanks!