Case statement question

[hithesh123]

Let's say you have a simple case statement -

case  SEL is
          when  "00" => output1 <= "0010";
          when  "01" => output1 <= "0011";
          when  "10" => output1 <= "0101";
          when  "11" => output1 <= "0110";               
          when others =>  output1 <= "0111";
end case;

This will be infered as a Mux when synthesised.

But what if I do this case statement under the rising edge of a clock.

If (rising_edge) then

Case ...
..

What would the infered logic be?

 

[TrickyDicky]

it will be a mux that has a register after it.

 

[Toneski_IP]

Succinct answer.....

I would have thought it would actually synthesize down to 4 LUTs & 4 FF's

Sorry to be pedantic...:lol: