Case statement inside if-else in verilog

[sun_ray]

Can a case statement be written inside the if-else statement in Verilog? For example, can the case statement be inside the else part of an if-else statement?

Regards,

sun_ray

 

[tipu_sultan]

Yes you can use case statement within else if statement in Verilog format.
I also believe that in Verilog the if-else statement not used generally.

 

[dave_59]

I also believe that in Verilog the if-else statement not used generally.

Where did you hear or read that? You can mix them any way you choose.

 

[sun_ray]

But if I have an if else statement for a sequential circuit like. flip flop or any other sequential circuit. Can we nest case statement inside that i--else statment by writing a case statement inside the else portion?

Regards

 

[FvM]

In terms of the Verilog LRM, a conditional or case statement can be used in place of a simple statement (See A.6.4 Statements) This already answers your question.

 

[sun_ray]

FVM

I do not have the LRM now open in front of me. Can you please let me know what this simple statement mean?
Can you also please answer my question directly?

Regads