I am now doing STA with primetime
test enable signal is SCAN_MODE
one clock signal is generated in interior through a XNOR cell
another input signal of the XNOR cell is a signal that propagated from SCAN_MODE(it sticks to 0)
so i think the phase of the clock is the same with the input clock,
but when report_timing, one path start point is not from time 0,
for example the clock period is 20, we created the clock as
create_clock clock [get_port clock] -period 20 -waveform [list 0 10]
when report_timing, the start point is from the rise edge of the clock, that is time 10, not 0, why,(the end point of the path is the output port of the chip, the expected arrive time is 20)
I check the other input of the xnor with report_case_analyasis -all
it exactly is 0. so the case analysis signal does propagate to the xnor, why?
thanks