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cascode structure for PSRR improvement in Bandgap and LDO

deep_sea

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Hi fellows,
I would like to know why the cascode topology improves the PSR of the bandgap reference? Is it because there is high impedance path that attenuates the power supply noise?
Also in LDO, does the cascode topology in error amplifier provide the same advantage?
 

dick_freebird

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Lambda is a limitation to PSRR in simple circuits.
Adding headroom increases all drain currents in
current mirrors, gain stages.

Cascodes produce a quasi-constant headroom
on key current source / mirror devices.

Cascodes are not a panacea. Sometimes the
node in question may be sensitive to the
cascode device's capacitance (to where?) and
really wants "pinned" to the other rail somehow.
For example if you are driving the PMOS pass
FET with a cascode NMOS its Cdb (in vanilla
CMOS) is ground referred and supply activity
will push HF "stimulus" into the gate. The
same is true of a simple mirror, but the cascode
probably has flattened the I-V characteristic
and made the gate node very high impedance,
pulling the pass FET pole to lower frequency
(gate drive less effective @ HF, so the error amp
becomes ineffective as a HF PSRR actor).
 

justanavgme

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Hi fellows,
I would like to know why the cascode topology improves the PSR of the bandgap reference? Is it because there is high impedance path that attenuates the power supply noise?
Also in LDO, does the cascode topology in error amplifier provide the same advantage?
I'm a newbie here. But I've just did my design project on LDO in the last semester so I'll try to explain what I understand.

For low frequency region (DC to a few kHz), the LDO's PSRR is directly proportional to your Error Amplifier (EA)'s open loop gain A. Here's the equation I took from a very helpful app note published by Toshiba:

PSRR = 20 log (AB), (approximated for low freq range, B is the feedback factor of your circuit)​

So in my opinion, having a cascode/folded-cascode EA will simply boost the EA's open loop gain, thus improving the overall PSRR of your LDO.

I prefer to over-design my EA with very high open loop gain and then have an easier time working with my LDO's PSRR later on.

Another common method to improve your PSRR is to use an N-MOS pass transistor instead of a P-type one. However, this requires and additional Charge Pump circuit so will increase your design's complexity.
 

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