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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 library IEEE; process(a, b, cin,clk) variable P: STD_LOGIC_VECTOR (N downto 0); variable C: STD_LOGIC_VECTOR (N downto 0); variable P_block: STD_LOGIC_VECTOR (N downto 0); variable C_block: STD_LOGIC_VECTOR (N downto 0); variable CO_block: STD_LOGIC_VECTOR (N downto 0); variable s: STD_LOGIC_VECTOR (N-1 downto 0); begin C(1) := (a(0) and b(0)) or ((a(0) xor b(0)) and cin); s(0) := a(0) xor b(0) xor cin; for i in 1 to K-1 loop ---------------------calculate the first block with k bit of adder C(i+1) := (a(i) and b(i)) or ((a(i) xor b(i)) and C(i)); ---calculate the carry out of the first block s(i) := a(i) xor b(i) xor C(i); -- calculate the sum of the first block C_block(i) := c(i+1); --the carry out for the first block end loop; for i in 1 to R-1 loop -----calculate the blocks for i in 0 to k-1 loop --calculate the blocks for k bits if ( rising_edge(clk) ) then C_block(i+1):= (a(i) and b(i)) or ((a(i) xor b(i)) and C_block(i)); if ( rising_edge(clk) ) then s(i) := a(i) xor b(i) xor C(i); if ( rising_edge(clk) ) then P(i) := a(i) or b(i); if ( rising_edge(clk) ) then P_block(i) := P(i); if ( rising_edge(clk) ) then P_block(i) := P_block(i) and P(i); --calculate the propagation for the block end if; end if; end if; end if; end if; end loop; CO_block(i) := (P_block(i) and C_block(i+1)) and C_block(i+k) ; --calculate the carry in for the next block end loop; Cout <= CO_block(R); --the carry out of the last bit sum <= s; --the total sum end process; end behavioral;

ERROR:Xst:827 - "H:/carry skip adder/carryskipadder/carryskipadder.vhd" line 41: Signal s<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Can anyone tell me what is problem in code

Thanks

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