# Carry skip adder error in VHDL

Status
Not open for further replies.

#### Arrowspace

##### Banned  Code VHDL - [expand]1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
library IEEE;
process(a, b, cin,clk)

variable P: STD_LOGIC_VECTOR (N downto 0);
variable C: STD_LOGIC_VECTOR (N downto 0);
variable P_block: STD_LOGIC_VECTOR (N downto 0);
variable C_block: STD_LOGIC_VECTOR (N downto 0);
variable CO_block: STD_LOGIC_VECTOR (N downto 0);
variable s: STD_LOGIC_VECTOR (N-1 downto 0);

begin

C(1) :=  (a(0) and b(0)) or ((a(0) xor b(0)) and cin);
s(0) := a(0) xor b(0) xor cin;
for i in 1 to K-1 loop      ---------------------calculate the first block  with k bit of adder     C(i+1) :=  (a(i) and b(i)) or ((a(i) xor b(i)) and C(i));   ---calculate the carry out of the first block
s(i) := a(i) xor b(i) xor C(i); -- calculate the sum of the first block
C_block(i) := c(i+1);   --the carry out for the first block
end loop;

for i in 1 to R-1 loop  -----calculate the blocks
for i in 0 to k-1 loop      --calculate the blocks for k bits

if ( rising_edge(clk) ) then

C_block(i+1):=  (a(i) and b(i)) or ((a(i) xor b(i)) and C_block(i));

if ( rising_edge(clk) ) then

s(i) := a(i) xor b(i) xor C(i);

if ( rising_edge(clk) ) then

P(i) := a(i) or b(i);

if ( rising_edge(clk) ) then

P_block(i) := P(i);

if ( rising_edge(clk) ) then

P_block(i) := P_block(i) and P(i);  --calculate the propagation for the block

end if;
end if;
end if;
end if;
end if;

end loop;

CO_block(i) := (P_block(i) and C_block(i+1)) and C_block(i+k) ; --calculate the carry in for the next block
end loop;
Cout <= CO_block(R);    --the carry out of the last bit
sum <= s;   --the total sum
end process;
end behavioral;

ERROR:Xst:827 - "H:/carry skip adder/carryskipadder/carryskipadder.vhd" line 41: Signal s<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Can anyone tell me what is problem in code

Thanks

Last edited by a moderator:

#### sharath666 What is "i" doing outside the for loop. Moreover C(0) is not defined...

#### TrickyDicky There are too many clock statements in the code that is causing the failure. Asside from that, the code is terrible.

I highly suggest you find a VHDL textbook or tutorial and start again.

##### Super Moderator
Staff member This code looks like you thought out the algorithm as you would in a software program, and then used VHDL to write the software. This code isn't based off a schematic design, and therefore this code doesn't describe anything that can be implemented in hardware. As Tricky says read a VHDL book and check out tutorial websites like [url]https://asic-world.com/index.html[/URL], which has examples in both VHDL and Verilog for basic functional blocks.

Basically you need to start over with timing diagrams and a schematic design either drawn out or "visualized in your head" that represents the circuit you are trying to implement. Then write the description of that circuit in VHDL.

#### Arrowspace

##### Banned Hello ads-ee, thanks for VHDL tutorial link, In simulation I have to force clock to get timing in simulator. How can i generate of 0.02usec in code.

- - - Updated - - -

can someone tell me how it's working

monitor : PROCESS (clk)
variable c_str : line;
begin
if (clk = '1' and clk'event) then
write(c_str,count);
assert false report time'image(now) &
": Current Count Value : " & c_str.all
severity note;
deallocate(c_str);
end if;
end PROCESS monitor;

end counter_tb;

#### TrickyDicky This is a very simple process - on every clock cycle, it outputs the current time and the current value of the "count" signal.

#### Arrowspace

##### Banned I am getting new error.

ERROR:HDLCompiler:24 - "H:/Sequencial_filter/filter_tb.vhd" Line 101: write expects 2 arguments
ERROR:HDLCompiler:541 - "H:/Sequencial_filter/filter_tb.vhd" Line 101: Type void is not an array type and cannot be indexed.
ERROR:HDLCompiler:854 - "H:/Sequencial_filter/filter_tb.vhd" Line 42: Unit <behavior> ignored due to previous errors.

#### Attachments

##### Super Moderator
Staff member Refer to a post by Tricky: https://www.edaboard.com/threads/253386/#post1084810
as you never post full code in syntax tags we can only assume you probably did something wrong somewhere else in your code that you didn't post.

FYI posting everything as a screen capture isn't going to make it easy for anyone to help you. As we are all volunteers making it difficult to test any code you provide in a screen capture isn't going to win any favorable responses. I certainly wouldn't try typing in your code from a screen shot.

#### Arrowspace

##### Banned Code:
   -- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for Clk_period*10;

-- insert stimulus here

wait;
end process;

monitor : PROCESS (clk)
variable c_str : line;
begin
if (clk = '1' and clk'event) then
write(c_str,Yout);
assert false report time'image(now) &
": Current Count Value : " & c_str.all
severity note;
deallocate(c_str);
end if;
end PROCESS monitor;

END;

Last edited:

##### Super Moderator
Staff member #### Arrowspace

##### Banned I am trying write() function for signed is this possible.

Code:
COMPONENT fir_4tap
PORT(
Clk : IN  std_logic;
Xin : IN  signed(7 downto 0);
Yout : OUT  signed(15 downto 0)
);
END COMPONENT;

#### TrickyDicky The first thing to note that Yout is an output so you cannot read it's value in VHDL '93

Also, there is no native write function for the unsigned or signed types in VHDL '93. You'll have to convert them to a type that is supported (like integer)

#### Arrowspace

##### Banned how can i convert signed to integer in VHDL

#### vGoodtimes TO_INTEGER (ARG: SIGNED) return INTEGER defined in ieee.numeric_std

#### Arrowspace

##### Banned Can you provide example for this

Code:
  Yout : OUT  signed(15 downto 0)

#### TrickyDicky We cant provide any example for an output, because an output cannot be read.

but for any signed

my_integer <= to_integer(my_signed);

#### K-J Can you provide example for this

Code:
  Yout : OUT  signed(15 downto 0)

Code:
  Yout : buffer signed(15 downto 0)

#### std_match Code:
  Yout : buffer signed(15 downto 0)

My advice is to not use "buffer". The biggest problem is when instantiating an entity with "buffer" type outputs. Such outputs can not be connected to normal "out" outputs. This means that all higher levels should use "buffer" instead of "out", which can be a big problem in a large project. Use an intermediate signal instead of "buffer".

Multiple drivers will be detected earlier with "buffer" outputs, but a simpler way to achieve that is to use std_ulogic instead of std_logic.

Status
Not open for further replies.