starrynight2020
Newbie level 1
Dear all,
I am new to vhdl and I just want to simulate carry look adder in vhdl.
I have wrote a code which implements this kind of adder ; however, this code do not works good with all test benches. Please note out put doesnot correspond to addition of inputs.
The code is in the following section.
I am new to vhdl and I just want to simulate carry look adder in vhdl.
I have wrote a code which implements this kind of adder ; however, this code do not works good with all test benches. Please note out put doesnot correspond to addition of inputs.
The code is in the following section.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY c_l_addr IS
PORT
(
x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-- carry_out : OUT STD_LOGIC;
G_STAAR : OUT STD_LOGIC;
P_STAAR : out std_logic
);
END c_l_addr;
ARCHITECTURE behavioral OF c_l_addr IS
--SIGNAL h_sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL g : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL p : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c : STD_LOGIC_VECTOR(3 DOWNTO 1);
--SIGNAL h_sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
g <= x_in and y_in;
p <= x_in xor y_in;
process (g,p,c)
begin
c(1) <= (carry_in and p(0)) or g(0);
c(2) <= (carry_in and p(0) and p(1)) or (g(0) and p(1)) or g(1);
c(3) <= (carry_in and p(0) and p(1) and p(2)) or (g(0) and p(1) and p(2)) or (g(1) and p(2)) or g(2);
end process;
sum(0) <= x_in(0) xor y_in(0) xor carry_in;
sum(1) <= x_in (1) xor y_in (1) xor c (1);
sum(2) <= x_in (2) xor y_in (2) xor c (2);
sum(3) <= x_in (3) xor y_in (3) xor c (3);
g_staar <= g(3) or (g(2) and p(3)) or (g(1) and p(2) and p(3)) or (g(0) and p(1) and p(2) and p(3));
p_staar <= (p(0) and p(1) and p(2) and p(3));
-- h_sum <= x_in XOR y_in;
-- carry_generate <= x_in AND y_in;
-- carry_propagate <= x_in OR y_in;
-- PROCESS (carry_generate,carry_propagate,carry_in_internal)
-- BEGIN
-- carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND carry_in);
-- inst: FOR i IN 1 TO 2 LOOP
-- carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND carry_in_internal(i));
-- END LOOP;
-- -- carry_out <= carry_generate(3) OR (carry_propagate(3) AND carry_in_internal(3));
-- END PROCESS;
--
-- sum(0) <= h_sum(0) XOR carry_in;
--
-- sum(3 DOWNTO 1) <= (h_sum(3 DOWNTO 1) XOR carry_in_internal(3 DOWNTO 1));
-- g_staar <= carry_generate(3) or (carry_generate(2) and carry_propagate(3))
-- or (carry_generate(1) and carry_propagate(2) and carry_propagate(3)) or
-- (carry_generate(0) and carry_propagate(1) and carry_propagate(2) and carry_propagate(3));
-- p_staar <= (carry_propagate(0) and carry_propagate(1) and carry_propagate(2) and carry_propagate(3));
END behavioral;
--
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--
----this is how entity for your test bench code has to be declared.
--entity testbench is
--end testbench;
--
--architecture behavioral of testbench is
----signal declarations.
--signal x_in,y_in,sum : std_logic_vector(3 downto 0) :=(others => '0');
--signal carry_in, carry_out,g_staar,p_staar : std_logic:='0';
--
--
--begin
----entity instantiation
--UUT : entity work.c_l_addr port map(x_in,y_in,carry_in,sum,g_staar,p_staar);
----definition of simulation process
--tb : process
--
--begin
--carry_in <= '1';
--x_in<="0000"; --num1 =2
--y_in<="0000"; --num2 =9
-- x_in<="1010"; --num1 =10
--wait for 2 ns;
--
--x_in<="0001"; --num1 =2
--y_in<="0001"; --num2 =9
--wait for 2 ns;
--
--x_in<="0011"; --num1 =2
--y_in<="0100"; --num2 =9
--wait for 2 ns;
--
--x_in<="0011"; --num1 =2
--y_in<="0001"; --num2 =9
----more input combinations can be given here.
--wait;
--end process tb;
--
--end;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity carry_lookahead_generator is
port ( g_star0 : IN STD_LOGIC;
p_star0 : IN STD_LOGIC;
g_star1 : IN STD_LOGIC;
p_star1 : IN STD_LOGIC;
g_star2 : IN STD_LOGIC;
p_star2 : IN STD_LOGIC;
g_star3 : IN STD_LOGIC;
p_star3 : IN STD_LOGIC;
c0 : IN STD_LOGIC;
C4 : OUT STD_LOGIC;
C8 : OUT STD_LOGIC;
C12: OUT STD_LOGIC;
g_starstar : OUT STD_LOGIC;
p_starstar : OUT STD_LOGIC);
end carry_lookahead_generator;
Architecture bahavioral of carry_lookahead_generator is
begin
c4 <= g_star0 or (c0 and p_star0);
c8 <= g_star1 or (g_star0 and p_star1) or (c0 and p_star0 and p_star1);
c12 <= g_star2 or (g_star1 and p_star2) or (g_star0 and p_star1 and p_star2) or (c0 and p_star0 and p_star1 and p_star2);
g_starstar <= g_star3 or (g_star2 and p_star3) or (g_star1 and p_star2 and p_star3) or (g_star0 and p_star1 and p_star2 and p_star3);
p_starstar <= p_star0 and p_star1 and p_star2 and p_star3;
end bahavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity CLA_16bit is
port ( x : in std_logic_vector (15 downto 0);
y : in std_logic_vector (15 downto 0);
c0: in std_logic;
s : out std_logic_vector (15 downto 0);
g_starstar : out std_logic;
p_starstar : out std_logic);
end CLA_16bit;
Architecture behavioral of CLA_16bit is
signal g_star0,g_star1,g_star2,g_star3,p_star0,p_star1,p_star2,p_star3 : std_logic:= '0';
signal c4,c8,c12 : std_logic:= '0';
begin
cla1 : entity work.c_l_addr port map(x_in => x(3 downto 0), y_in => y(3 downto 0) , carry_in => c0 , sum => s(3 downto 0), G_STAAR => g_star0,P_STAAR => p_star0 );
cla2 : entity work.c_l_addr port map(x_in => x(7 downto 4), y_in => y(7 downto 4) , carry_in => c4 , sum => s(7 downto 4), G_STAAR => g_star1 ,P_STAAR => p_star1 );
cla3 : entity work.c_l_addr port map(x_in => x(11 downto 8), y_in => y(11 downto 8) , carry_in => c8 , sum => s(11 downto 8), G_STAAR => g_star2 ,P_STAAR => p_star2 );
cla4 : entity work.c_l_addr port map(x_in => x(15 downto 12), y_in => y(15 downto 12) , carry_in => c12 , sum => s(15 downto 12), G_STAAR => g_star3 ,P_STAAR => p_star3 );
clg1 : entity work.carry_lookahead_generator port map( g_star0 => g_star0,g_star1 => g_star1,g_star2 => g_star2,g_star3 => g_star3,
p_star0 => p_star0,p_star1 => p_star1,p_star2 => p_star2,p_star3 => p_star3,
c0 => c0, c4 => c4,c8 => c8, c12 => c12,
g_starstar => g_starstar, p_starstar => p_starstar);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
architecture behavioral of testbench is
signal x,s,y : std_logic_vector (15 downto 0):= (others => '0');
signal c0,g_starstar,p_starstar: std_logic := '0';
begin
uut : entity work.CLA_16bit port map (x,y,c0,s,g_starstar,p_starstar);
tb : process
begin
x <= "0000000000001111";
y <= "0000000000000001";
wait for 2 ns;
x <= "0000000011110000";
y <= "0000000000010000";
wait for 2 ns;
x <= "0000111100000000";
y <= "0000000100000000";
wait for 2 ns;
x <= "1111000000000000";
y <= "0001000000000000";
wait for 2 ns;
x <= "0000000011111111";--problem in here!
y <= "0000000000000001";
wait for 2 ns;
x <= "0011110011111111";--and here
y <= "0000011000000001";
wait;
end process tb;
end behavioral;