Capturing Switching Activity Synopsys-Modelsim

[etherios]

synopsys modelsim

Ok Back again after so long. Happy new year to all of you.
I want to capture the switching activity of a ripple adder
I have the following files
the adder.vhd which describes the adder

library IEEE;
use IEEE.std_logic_1164.all;

entity adder is
port (
a,b,c :in std_logic;
sum,carryut std_logic);
end adder;

architecture adder of adder is
begin
sum <= a xor b xor c;
carry <= (a and b) or (b and c) or (c and a);
end adder;


and the adder_n.vhd which describes the rippler adder

library IEEE;
use IEEE.std_logic_1164.all;

entity adder_n is
generic (N: integer :=8);
port(
a,b:in std_logic_vector(0 to N-1);
cin:in std_logic;
sut std_logic_vector(0 to N-1);
coutut std_logic);
end adder_n;

architecture struct of adder_n is

component adder
port (
a,b,c: in std_logic;
sum,carryut std_logic);
end component;

signal c: std_logic_vector(0 to N);

begin
c(0)<= cin;
cout<= c(N);
adders: for k in 0 to N-1 generate
A1:adder port map(a(k),b(k),c(k),s(k),c(k+1));
end generate adders;
end struct;


i use the following script in synopsys
set search_path /home/kanagno/projects/hardware/adder
set link_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set target_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set symbol_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2.sdb
analyze -format vhdl adder.vhd
elaborate adder
analyze -format vhdl adder_n.vhd
elaborate adder_n
link
uniquify
compile
write -format vhdl -output synthesized.vhd

now how can i use the synthesized.vhd in modelsim in order to capture the switching activity of the design using a testbench file?

 

[elektor]

simulation synopsys modelsim

Hi,

You must have to VITAL primitives for your technological library ( eg. UMC)

In Modelsim you compile all of them first and next compile your netlist from DC.
At the end you compile testbench.
And :
1. Initalize simulation in MTI
2. vcd file your_name.vcd
3. vcd add /your_tb/* ( or -in, -out, -ports, -inout)
4. vcd flush
5. run (eg. 10 us)
6. quit -sim

and now you have your own .vcd file

Regards:
Elektor

 

[etherios]

switching activity file format

what do you mean with vital primitives?

 

[elektor]

modelsim vcd file size

Hi,

Vital primitives are special simulation libraries from library's vendor.
These libraries have information how behave simple elements during simulation
(eg. AND, OR , DFF )

Regards
Elektor

 

[etherios]

activity file for modelsim

ok i use the following flow and i like to ask your opinion
i synthesize the adder.vhd using the following script

set search_path /home/kanagno/projects/hardware/adder
set link_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set target_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set symbol_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2.sdb
analyze -format vhdl adder.vhd
elaborate adder
compile
report_cell
write -format vhdl -output synthesizedAdder.vhd

i use the following script to synthesize the adder_n

set search_path /home/kanagno/projects/hardware/adder
set link_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set target_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set symbol_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2.sdb
analyze -format vhdl synthesizedAdder.vhd
elaborate synthesizedAdder

analyze -format vhdl adder_n.vhd
elaborate adder_n
link
uniquify
compile
write -format vhdl -output synthesizedAdderN.vhd

then in Modelsim i create a project with synthesizedAdderN.vhd synthesizedAdderN.vhd and EXOR2D1, AO22D1 vitals
then i use the script elektor wrote
I have 2 questions
1. The adder cell is syntesized with Exor and Ao22 gates which means that in the adder cell there is an inner signal. Is the switching activity of this signal captured in the vcd file?
2. for a 8x8 multiplier with 200000 numbers as tests the generated vcd file is ~2GB what can i do to reduce the size?

P.S. elektor mate thank you

 

[elektor]

synopsys vital port generic

Hi,

Your script...
I think that will be better if you use script in this way :

(..)
analyze -format vhdl adder.vhd
analyze -format vhdl adder_n.vhd
elaborate adder_n
(..)

Ad 1.
Maybe Modelsim documentation help you.
Modelsim -> Command Reference -> vcd add

Ad 2.
First at all... Could you tell me why you need vcd file ? For Power's Analyze ?

 

[suituse]

vcd modelsim switching activity

Excuse me, I also have a few questions.

1) If I use the vcd file to do power analysis, which vcd command should I use ? the "vcd add" or the "vcd dumpports" ? It was said that the vcd file generated by the former doesn't contain the strength info (only the 0\1\X\Z) but the latter does.
Is the former enough for power analysis?

2) And as for power analysis, the detail activities of the gates in all modules should be capture, can i use this command : vcd add -r -file design.vcd /test_bench/dut/* to capture the signals in all region?

Thank you for telling me about that

 

[etherios]

modelsim vcd add power analysis

Ok according to manual vcd add captures the changes to internal variables.

All this fuss is because i want to import it to primepower

 

[elektor]

modelsim vcd add reference

Hi suituse,

Ad1. I use "vcd add" instruction. I know that "vcd add" generated vcd file in VCD format and "vcd dumpports" vcd file in EVCD format, but I dont think that Prime Power can use additional information from EVCD.
Big importance have good parasitic extraction (SDF) and clocks routing for power numbers.
Ad2
I think that you use this command properly.

Hi etherios,
You must to know that Power Analysis is based on arithmetical average all activites. Maybe you don't need all these tests for reality power numbers.
Other solution is use .fsdb file format instead of .vcd file.
But in this case you need Debussy nWave soft .

Regards:
Elektor

 

[etherios]

prime power link db synopsys

the problem is that power is also up to the spatial-temporal dependence of the inputs so in order to measure the exact power you need this kind of simulation.

If anyone knows what can i do with the size of vcd file plz tell me