Capacitor mismatch in sampler/DAC

[anindya1012]

How does capacitor mismatch depend on the value of the capacitor? Is it the same as mosfets i.e. with increase of area the mismatch reduces? If I am not limited by kT/C noise in sampler (my design has multiple samplers), can I go arbitrarily low with the value of the capacitor or is it limited after a certain resolution?

 

[AMS012]

Capacitor mismatch reduces when the area increases. It is the same as MOS.

The lowest value of the cap that you can get depends on your process technology, i.e the least width the metals can have. (I assume you are using metal caps and not mos caps for sampling)

 

[anindya1012]

Thanks AMS012. My question is: I heard from some source that it is not good to go below 100fF (let's say I want a 12 bit resolution), as the capacitor mismatch will limit the resolution. Is this statement true? How do I quantify the mismatch? is there a formula for mismatch like we have for MOS?

 

[AMS012]

Generally, foundry gives a process document containing the standard deviation of mismatch for all the components like cap, mos and resistors etc. Using this SD numbers, you must be able to simulate the capacitor mismatch effect with the help of a simulator(Mismatch simulations are called Monte Carlo Simulations).