Capacitor bank pex in sar adc

[Amr.Ibrahim]

Hello All,

I am designing 12 bits asynchronous sar adc 10Mhz sampling frequency and I am done with the layout and it works good with pex but C only (I mean that I extract only capacitor not resistance) but when I tried to extract RC pex the enob became worse about 2 bit less so I am asking what will affect my enob I mean these resistors added by extraction or what?

Thanks in advance.
Regards,
Amr

 

[erikl]

... when I tried to extract RC pex the enob became worse about 2 bit less so I am asking what will affect my enob I mean these resistors added by extraction ...?

May be RC delay effects. Did you try and sample with a lower frequency? Try with 1 MHz e.g. and compare ENOB.

 

[Amr.Ibrahim]

May be RC delay effects. Did you try and sample with a lower frequency? Try with 1 MHz e.g. and compare ENOB.

I didn't try to reduce the frequency but ok I will try. I plot the input of the comparator and I saw that it settled correctly so I think it is not settling issue.