capacitive effect between two traces

[bondadoso]

from how frecuency (MHZ) should I worry about the capacitive effect between two wires.

i have to divide 200 mhz signal with a prescaler by 256 to have a 781,250 hz signal and to put in to a adc.
so i need special considerations for the pcb :?:
if someone give me a books or references i will be grateful

 

[marce]

If this is a clock, use the following rules:
Std trace to std trace = 1x
Clk trace to any other trace (except GND) = 3x
Clk trace to GND = 1x
Where 1x = track to track spacing for the design (so if T to T = 0.1mm, for the clock it would be 0.3mm)
This will always allow you to put a guard trace around the clock signal if required, if not the 3X the normal spacing will minimise capacitive and inductive coupling.