Capacitance effect due to more vias and metal straps.

[reddvoid]

L1 output pin  uses M1 for output pin + 2M0 vias to M0 straps
L2 output pin  uses M2 for output pin + 6 M1Vias to 6 M1 straps + 12 M0 vias to M0 straps  lower cap than L1

L1 input pin  uses M0 layer
L2 input pinuses M1 layer 1 M0 via to M0  lower cap than L1

I have these two layouts, both are of same size (INVERTER LAYOUTS)
though L2 is using more straps and vias in addition to what L1 is using, I am seeing lower caps on input and output nets of L2, when I do the extraction in virtuoso.

I expected higher caps on input and output nets in L1
am I missing something? , Higher layers have lower cap, but L2 is using higher layers plus the layers used by L1 , so clearly I was expecting higher caps in L2
am I missing something or its due to some messup in extraction ?

Thank you.

 

[reddvoid]

L1 output pin --> uses M1 for output pin + 2M0 vias to M0 straps
L2 output pin --> uses M2 for output pin + 6 M1Vias to 6 M1 straps + 12 M0 vias to M0 straps --> lower cap than L1

L1 input pin --> uses M0 layer
L2 input pin-->uses M1 layer 1 M0 via to M0 --> lower cap than L1

I have these two layouts, both are of same size (INVERTER LAYOUTS)
though L2 is using more straps and vias in addition to what L1 is using, I am seeing lower caps on input and output nets of L2, when I do the extraction in virtuoso.

I expected higher caps on input and output nets in L1
am I missing something? , Higher layers have lower cap, but L2 is using higher layers plus the layers used by L1 , so clearly I was expecting higher caps in L2
am I missing something or its due to some messup in extraction ?

Thank you.

Updated question

 

[ranaya]

I expected higher caps on input and output nets in L1

Are you referring to the total input/output caps seen through these pins ? What are the NMOS/PMOS sizes used in these two layouts ? In which technology ?

Anuradha