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Capacitance as a specification for DDR2, DDR3

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ZincBear

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Dear experts,

There is a burning question that has been bothering me.

When i looked through the JEDEC standards for memory such as DDR, DDRII and DDRIII, i always see this specification for pin capacitance for the various address and data pins. Why is this so?

Given that these people are concerned with timing diagrams and eye diagrams, how does this pin capacitance affect compliance of memory chips?


Kindly share any insight..thanks!
 

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