[SOLVED] Can't we use initial statement in interface block in system verilog?

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u24c02

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Hi.

When I use initial statement in interface block in systemverilog, it have some compile error.

Can't we use inital statement in interface block?
 

You can certainly use initial or always blocks inside an interface. Please provide the error.
 

The error message is following that ' a clocking output must be driven by a clocking drive'

Why is the error happening?
Code:
clocking cb@ (posedge clk);
Output data, read , addr;
Read enable;
Endclocking

...

Module tb(...)
initial begin
...
tb.cb.read  = 1 ;
...
End

I found it.
It should be <= not =..the reason but I don't know.
 

Your error message had nothing to do with initial blocks.

See 14.16.1 Drives and nonblocking assignments in the 1800-2012 LRM for an explanation of the syntax.
 

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