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can't define verilog module

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siva_7517

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icfb verilog®-xl

hi all,

There is a error when import my optimized design to icfb. Because of this error, i cant open verilog xl to do gate level simulation. need some idea's on this.

siva
 

jjww110

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define verilog

please give more detail message!!
 

aji_vlsi

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siva_7517 said:
hi all,

There is a error when import my optimized design to icfb. Because of this error, i cant open verilog xl to do gate level simulation. need some idea's on this.

siva
What is the error message? Simply saying "There is a error " - doesn't give a hint.

Learn how to ask the right questions to get the right answer/help.

Ajeetha
www.noveldv.com
 

siva_7517

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hi guys,

Sorry for not including the error statement.
There is an error statement in icfb log file when i have import my optimized verilog design to icfb. There error statement is:

Verilog defination for module INVX1 was not found. Using lib 'silterra18' cell 'INVX1' view 'symbol' as its symbol

Because of this statement i cant open this verilog design file in verilog xl to do a gate level simulation.

Siva
 

aji_vlsi

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siva_7517 said:
hi guys,

Sorry for not including the error statement.
There is an error statement in icfb log file when i have import my optimized verilog design to icfb. There error statement is:

Verilog defination for module INVX1 was not found. Using lib 'silterra18' cell 'INVX1' view 'symbol' as its symbol

Because of this statement i cant open this verilog design file in verilog xl to do a gate level simulation.

Siva

Siva,
I've not used icfb etc. But looking at name of this INVX1, it is clear that it is an inverter. For plain Verilog sim, it is trivial to define it yourself and pass it as additional file to VXL.

module INVX1(..); // input/output
assign my_out = ~my_in;
endmodule

Of-course best will be to fix your flow (via icfb).

Regards
Ajeetha
www.noveldv.com
 

leeenghan

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Hi,

There are 2 parts to the answer to your question.

1. When you read a verilog netlist into icfb, you need to define the reference library that contain the standard cell (e.g. INVX1).

2. You do not need to read the verilog netlist into icfb to do simulation. I think nobody does this. You just run you simulation outside icfb environment. What do you wish to achieve by reading the netlsit into icfb that you cannot achieve by not doing this step?

Regards,
Eng Han
www.eda-utilities.com
 

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