Cannot resolve indexed name as type ieee.std_logic_1164.std_logic_vector

[anonymous.]

I have a component with generic.

component DCache_SinglePortRam is
		generic (Width : integer := 32;
			 Length : integer:= 256);
		port(Clk: in std_logic;
	    	     WordLine : in std_logic_vector(Length-1 downto 0);
	    	     DataIn : in std_logic_vector (Width-1 downto 0);
	    	     DataOut : out std_logic_vector (Width-1 downto 0);
	    	     RW : in std_logic);
	end component;

and I have those signals defined :

	signal LRU_BankRead : std_logic_vector(NumOfPorts-1 downto 0);
	signal LRU_BankWrite : std_logic_vector(NumOfPorts-1 downto 0);

Sometimes I need to use the component with the generic Width = 1 as follows :

LRUBank : DCache_SinglePortedRam
				generic map(1,LengthOfBank)
				port map(Clk,WordLines(i),LRU_BankWrite(i),LRU_BankRead(i),LRU_RW(i));

which when compiling in modelsim results in this error for LRU_BankWrite and LRU_BankRead signals (or places in the port map):

Cannot resolve indexed name as type ieee.std_logic_1164.std_logic_vector

I have encountered this error before and solved it by using a different component with std_logics and no generics instead of std_logic_vectors.
unfortunately this is not possible here, Is there any other way around it ?

 

[barry]

You're not showing what Wordlines(i) is. Is WordLines an array of std_logic_vectors? Not sure you can do that since you've dimensioned WordLines in the component using a generic. That may just be a limitation of VHDL. Does this only fail when you use "1" for your width? I've run into problems (specifically with vendor IP) where they'll have

x=std_logic_vector(0 downto 0);

which would cause compile failures.


Maybe something like this would work:

dummy:std_logic_vector(width-1 downto 0);
.
.
dummy<=Wordlines(i);
port map(Clk, dummy...)

BTW, you need a better name than "anonymous".

 

[rca]

which is the relation between "NumberOfPorts" and "Width"?