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cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

chyavanphadke

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I wrote a Verilog code for DE-10 Lite in Quartus Prime, I am getting the error it says "cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct". Can you please help?

Code:
module DemoBlink (

    input clk, rst,

    output [9:0] LED

);


reg [24:0] counter;

reg [9:0] temp;


initial begin

    temp <= 1'b0;

    counter <= 0;

end


always @ (posedge clk or posedge rst) begin

  

    if (!rst) begin                                                          // Error is in this line

        temp <= 1'b0;

        counter <= 0;

    end else begin

        counter <= counter + 1;

        if (counter == 8'd25000000) begin

            temp = ~temp;

        end

    end

end



assign LED[0] = temp;


endmodule
 
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vGoodtimes

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verilog synthesis uses the sensitivity list and code to determine clock vs reset. This avoids the need for an "if rising_edge(clk) then" line.

so in this case, you have "posedge rst" which doesn't match the "if (!rst) begin".
 

chyavanphadke

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verilog synthesis uses the sensitivity list and code to determine clock vs reset. This avoids the need for an "if rising_edge(clk) then" line.

so in this case, you have "posedge rst" which doesn't match the "if (!rst) begin".
@@vGoodtimes, thanks for the explanation. I understood and did accordingly it worked.
 

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