Can you synthesize a VHDL and Verilog mixed design?

[verma.ind]

Can we write design in both verilog and vhdl means one module of that design in verilog and other in vhdl? Can it be possible?
Can we synthesize these type of design?

Thanks

 

[aji_vlsi]

Re: VHDL and Verilog

Can we write design in both verilog and vhdl means one module of that design in verilog and other in vhdl? Can it be possible?
Can we synthesize these type of design?

Thanks

Yes, this is the need of the day with all IPs and SoC era.

Ajeetha, CVC
www.noveldv.com

 

[omara007]

Re: VHDL and Verilog

Can we write design in both verilog and vhdl means one module of that design in verilog and other in vhdl? Can it be possible?
Can we synthesize these type of design?

Thanks

Yes you can, but you will need to have all your tools supporting mixed language .. for example, your HDL simulator should support mixed languages designs ..