use a frequency synthesizer circuit like a pll.but it also depends where u wnat to use this clock multuiplier.for applications where jitter is critical u may be forced to use a delay locked loop multiplying circuit and for other applications where some jitter can be tolerated,u can go in for a PLL.
Hi,
I think what abhineet22 wants is this. He is talking about a digital circuit
that has a signal say sig_in which is just pulsese with some width 'w' and
he wants to sample this with his clk and generate o/p which lasts for N clock
cycles. This can be done in following two ways ....