Can you route this better than I can?

[torinwalker]

Routing two x16-wide chips has turned out to be more complex than I had hoped. I've taken a break before routing the remaining ratsnest to post this message.

I'm trying to wire up two DDR SDRAM chips, one per chip select on a PXA310 processor. These are x16-wide chips MT chips with 15 address lines. If I use only one chip, the process is relatively easy, but I lose half of my memory. In this day and age, memory is everything. I can't afford to chop the memory in half to 128M by using only one chip. Well, actually, I can afford to, but I don't want to. It's like building a Mustang with a four-cylinder engine - looks great on the outside, but the test drive has you wanting for something with more power.

The processor design guide suggests a max 1.1" total trace length between chips, and also suggests a balanced T layout. It also suggests using the two top layers. It also suggests, and suggests, and suggests. This design is highly constrained.

What you see here is my first attempt to lay out the chips. The autorouter just made a big mess, which is why I'm doing it by hand. Perhaps that is the usual case, but this is my first modern design - I'll thank you to humour me with what I'm doing here.

The layout and pinouts, including the density of these chips (0.5mm) makes it difficult to break out and keep everything on two layers.

I'm interested in your opinions on how this could be done better. Yes, I am aware that the trace lengths in each byte lane have yet to be matched. I can also imagine that the extra vias may cause ringing. It kinda looks old school, doesn't it?

Would it be considered bad form at this point to introduce a third (and possibly fourth layer) to route address and control lines? Data would be on the top two layers, (ground is layer #3) and address, control, and clocks would be on layers 4 and 5.


Torin...

 

[FvM]

I generally doubt, that the two RAM chips can be connected using two signal layers.

Apparently, the SSTL interface is operated without termination. Normally, SSTL is using matched 50 ohms transmission lines, it could be routed to inner layers at matched impedance. Ommitting all termination resistors except for driver internal series termination is a method to simplify a design but also restricts it to small dimensions.

In this case, it's impossible to follow general DDR RAM interface rules, e. g. from manufacturers. But if you are using routing segments at layer 2, you could use bottom layers in addition, or are you also constrained to use blind vias?

Regarding autorouter application, I think e. g. Specctra could be used with a lot of fromto rules to achieve the T-connected topology.

 

[torinwalker]

FvM,

Your insight helps me quite a bit.

To reduce design time, I leveraged portions of a reference design that happened to omit termination. The design guide for this chip additionally states that the drive levels are programmable, eliminating the need for external termination. I am also learning from the design files (Cadence PCB files) about how to lay out an actual cellphone design. It's too bad their design only has one SDRAM chip.

Do you think that by terminating externally I might be able to drive much longer lines? If so, I have plenty of real-estate for the endeavour, but I'll have to go back and better understand the driver mechanism. Longer lines might give me more freedom to spread these chips apart further and also to route lines the long way around the backs of these chips. It'll also give me the wiggle room that I clearly have yet to incorporate.

The design guide suggests that lines should be routed on the top layer and impedance controlled to 90 ohms +/- 10%, and/or on the second layer (buried microstrips) and controlled to 60 ohms +/- 10%. Aside from having to weave traces around the decoupling capacitors on the bottom side, I have no reason not to try the two layers an the bottom. I'll give your suggestion a try tonight.

Regarding from-to rules. Altium happens to have a fromto rules section in its rules setup. I noticed them last night but didn't immediately understand their application. I'll take another look again to see how I can employ them.

If one establishes all the proper rules for impedance, length-matching, byte-lane net grouping, from-to rules, and so forth, is it reasonable to expect that an autorouter should be able to route the memory by itself? Or, is it generally expected that (even with today's technology) that routing memory is still very much an interactive task?

I don't mind if the latter is the case, but knowing, as they say, is half the battle. I don't know if I should be trying to route this manually, or if I should be trying instead to create proper rulesets so that the autorouter does the work.

Thanks, FvM.


Torin...

 

[FvM]

Hello Torin,

basically the SSTL IO-standard used with DDR Ram is intended to drive terminated mached impedance lines with a certain length, at least the 6-8" usually found in a PC motherboard. I guess that the PXA310 uses DDR standard, not DDR II? By specification, they use a single ended parallel termination at the memory side plus a source side driver impedance matching. In this case, two chips on a bus would be better arranged in line than star- (or T-) connected. Details can be found in memory manufacturer's documents, e. g. Micron has some good application notes.

The most difficult task, however, is impedance matching with bidirectional DQ and DQS lines. Achievable signal quality partly depends on the PXA memory interface properties.

I wonder, if in your case the originally suggested method may be still applicable, if necessary using more layers to connect both chips. But the T-connections are a compromise that can work only with very short stubs. Thus you should try mostly to make the memory bus small.

Frank

 

[torinwalker]

Frank,

This is what the design guide suggests for using two chips, one per chip select. All common lines are routed according to this diagram. One could infer from this design a T, but more likely a daisy chain. TL1 is the breakout from CPU to the first via. TL2B (don't ask me why B comes before A) is the first stretch of signal to the memory layout area. At this point, TL3B connects to chip B (this is the breakout trace from that chip), but TL2A continues. Finally, TL3A (chip A's breakout) connects the trace to the pin.

Using your suggestion, I think I'll try the daisy-chain (in-line or bus) approach instead.

What about routing? Should I do this manually, or should I configure the rules and let the autorouter do its job? How would you go about doing this?


Torin...

 

[FvM]

Yes, apparently the TL3x symvbolize the necessary escape routing rather than suggesting a star topology. The difference is in the real segment lengths, of course. Did you see the Micron DDR application note? It discusses a full termination scheme for a two chip design.https://download.micron.com/pdf/technotes/TN4607.pdf

Personally, I would try to use an autorouter. You should be able to constrain it exactly, regarding topology and also routing layers. But I'm not sure about the result. When I see e. g. PC mainboards, there's a lot of handwork usually.

 

[torinwalker]

I spent quite a bit of time trying to get the autorouter to route even one chip, and it would usually give up before completing. Granted, it might have if I spent even more time with it, but at that point I gave up and decided to try my hand at this one more time.

This time, I used only one chip, and I tuned every single signal to 27mm +/- 0.1 millimeters (a tenth of a millimeter), roughly. There will likely be more variation between the signals due to the difference in vias and whether the shunt to the same side or the opposite side.

I'm posting my work in the hope that you might constructively criticize my routing job. Note, this is my first high speed DDR routing job. The memory is routed using four layers. The D[15:0], DQM[1:0], and DQS[1:0], SDCLK_P and SDCLK_N were routed mostly on the top two layers (1 red & 2 yellow) near the ground plane (3 not shown). The address and control were routed on the bottom two layers (9 violet & 10 blue) near the power plane (8 not shown).

Matching lengths while keeping the distances below 1.1" (approximately 27mm) made it difficult to spread out the signals. Consequently, everything is packed into this tight little area. I still have some tuning left to do - for example, distributing the squiggles better so they don't overlap, and adjusting the spacing of the signals from one another.

Otherwise, I'm very interested to hear your opinion. I'm especially concerned about the inductance.

Also, which approach do you think is better, the first or the second?


Torin...

 

[FvM]

I think, the first one was better for a simple reason. I basically doubt, if delay tuning below a delta of 100 ps (30 mm trace length) would be needed here. What's the intended memory clock? It consumes a lot of board space and should be used carefully without screening of adjacent signal layers, cause it increases the coupling considerably.

 

[torinwalker]

Too bad. I worked hard on that layout!

I'll go back to the original strategy and try it again, but this time I'll route only one chip. I also think I can re-order the traces to eliminate one via from each line.

Once I've laid out the first one, I'll use the bottom two layers to daisy-chain the second IC.

I'll keep you posted.


Torin...

 

[FvM]

Yes, sorry for that. Please notice, that I just express my opinion in this matter (respectively tell, what I would do). I have technical arguments of course, but other PCB design experts may think different about.

Good luck.

 

[euanl]

A couple of possibilities - can you pin swap the processor to untangle the nets? Also does the chosen memory come in a reversed pin out that would let you mount one on the top and one on the bottom with minimum stubs from the T point. Just some thoughts!

 

[torinwalker]

You know, I was thinking exactly the same thing. There must be a complimentary set of memory modules whose pins are the upside-down mirror of one another. I've had my heart set on these MT chips because of their 1Gbit density, but what's the use if I can only use one??

Here's my next attempt. This time, I routed the lines as straight as possible, and I got the chip much closer to the processor this time. This is essentially a variant of the inductive mess I created earlier, but with all the delay lines, ehm, removed.

Naturally, I had to do something about the widely varying lengths. The design guide suggested +/- 0.1". I had to come close, at least. Now the tolerances are much lower and there's much less coupling than before. This is how I originally wanted to do it, but I guess I needed to practice to get to this point!

Note: There are a few lines I missed. It's getting late and my wife is calling me. I'll finish the rest tomorrow, barring of course, your countering wisdom.


Torin...

 

[torinwalker]

Oh, I forgot to ask: Since you mentioned it, do you happen to know which manufacturer makes complimentary sets of DDR SDRAM packages?

 

[FvM]

Looks much better now. Regarding timing matching, I understand that the +/- 0.1" specification is within a byte lane usually, tolerances may be higher for some memory controllers.

Double sided assembly is what I generally use to compact designs, if applicable. I'm not aware of DDR RAM with mirrored pin mapping, I think this an option for modules only. But also back to back assembly of regular chips (with a small offset for better via placement) gives shorter stubs than placing the chips side by side.

 

[torinwalker]

Yes, the restrictions are for the byte lanes. Although they appear similar, I length-matched data[7:0] to dqm0 and dqs0, and separately matched data[15:8] to dqm1 and dqs0. The address lines are matched to each other, and the clock was specified as being equal to the address lines, up to 1.6".

When I finish the layout and run SI on the lot, I will post my results.

Thank you, Frank. You've been a big help. I won't forget.


Torin...