Can you build an on-chip LDO ?

[jayateertha.r]

Hi,

I am designing a LDO which has load onchip.

Although I have a big off chip capacitor(4.7uF), the bond pad inductance coming in series is affecting the load regulation transient. I am getting big spikes.

How to get rid of this problem? This must be a common problem as many chips will have a onchip LDO for a onchip load.

Is it possible to eleminate the offchip cap and build a LDO totally onchip?

thanks in advance.

regards,
jay.

 

[rfzheng]

onchip ldo

yes , of course, TI has a LDO without offchip CAP , the datasheet NO. is TPS73101,which is a capless LDO

 

[jt_rf]

on-chip ldo

rfzheng

Thanks for the reply. I went thru the TPS part no. It uses a nmos pass element in LINEAR.

I was just thinking, if there is an even simpler solution with PMOS pass element with some sort of compensation technique with small onchip (300pF) cap.

regards,
jay.

 

[sunilreddybvs]

replica bias using nmos driver

better to go for replica based architecture for bigger cap loads to avoid stability problems but it needs a bigger driver

 

[dhasmana]

site:edaboard.com capless ldo

Replica bias using NMOS driver has no stability problems but the dropout voltage will be more than a Vt if you are not using a cargepump to boost the regulator OTA supply voltage.

Regards,
Jitendra Dhasmana.

 

[hung_wai_ming@hotmail.com]

data sheet ldo load capless

jayateertha.r

Did u resolve the problem having bonding inductance? I am having the same issue as well, but it looks like we can't solve it.
However, the reality is I didn't see that spike in real silicon and I am still scratching head now

 

[niezimei]

capless ldo

It's easy to fix. Use Kelvin Connect

 

[mists]

Onchip LDO

may you explain detailly about "Kelvin Connect ", thanks!

 

[arghpok]

Re: Onchip LDO

How big is your series inductance ? Maybe 3 nH ? How heavy is your load ? You can reduce your overall inductance making thinner pads in parallel to the pin and/or with the multihole pad technique explained in detail in "Tha art of analog layout" from Alan Hastings. Can you upload your floorplan ? I might help you making a better one.

If you wanna make a capless LDO, you can make it using both the Active Miller capacitor multiplier techique developed by Rincon-Mora and the Compensation technique from Milliken. These techniques would lead you to an onchip cap of 100 pF or less.

PAZ PARA COLOMBIA !