Can we use Tanner software to design IC at CMOS level? In S-edit, NMOS or PMOS just have a few parameters like :W,L,PS,AS.. But in practical ,NMOS and PMOS have lot of parameters . So ,why we can design IC accurately?
Thanks a lots!
hi
actually only few parameters are of importance in calculations rest all make a very little difference that is why you can design accuratly with few important parameters
Hi!
When we simulate by Winspice,Hspice or Cadence NMOS and PMOS always be simulated follow a MODEL like (Level BSIM, MOSIS...). But in S-edit we can assign that Model into the circuit!
i think you misuderstood. S-Edit is use to draw schematic of the circuit. not simulate it. Tanner tools come in 4 software. S-EDIT, L-EDIT, W-EDIT, and LVS.
To simulate circuit. you need to extract the schematic drawn using S-EDIT into spice netlist. using this netlist, than you can simulate it using T-SPICE. however you need the SPICE model parameter like BSIM model. This T-SPICE is similar to HSPICE because both is SPICE simulation software. if you are familiar with HSPICE i thick you will find T-SPICE is similar and will not face trouble using it.
Sedit -> schematic tool like Cadence composer
or workview viewdraw or ECS (AMS/ADP)
Tspice -> like hspice/tspice
for ASIC design .. we use really aisc design tool
not Tanner .. ledit can layout fully chip . but fab only support dracula or calibre LVS/DRC command file , how to use Ledit is really ASIC design ??
you can use tanner to design IC. however when when you want to draw the layout you need fab design kit that support tanner software (L-EDIT) if fab house dont support that you have to manually setting all the layer/DRC in L-EDIT according to fab house process. then you need to write you own extract defination file in order to extract the layout into SPICE netlist. you can do all this thing manually but it is time consuming.