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All the asynchronous signals like reset , preset , clear are used for the purpose of sending the system into a known state in the initial condition. If reset is not used then definately flipflop output will be in any unknown state in the initial condition.
All the asynchronous signals like reset , preset , clear are used for the purpose of sending the system into a known state in the initial condition. If reset is not used then definately flipflop output will be in any unknown state in the initial condition.
If u don't use them the flipflop won't go into any metastable state. I think using an asynchronous signal itself may cause the system to go into this metastable state ???
[All the asynchronous signals like reset , preset , clear are used for the purpose of sending the system into a known state in the initial condition. If reset is not used then definately flipflop output will be in any unknown state in the initial condition.
If u don't use them the flipflop won't go into any metastable state. I think using an asynchronous signal itself may cause the system to go into this metastable state
kapil
this depend on what kind of design style you prefer to?
My experience is using DFFs with or without reset doesn't really matters. During
powerup, most FFs will have a know logic 0 or 1. But you have to know before hand
the uncontrollable output will cause any undesire effect or not.
For DFF with async reset, we can sure force them into know reset state. But for
DFF without reset, we can still use logic to control the output state(i.e. implement
sync reset using logic, which can be done using HDL & synthesis tools even if the
lib doesn't have any DFF with resets).
My concern is you have to make your reset signal a high fanout buffer tree or else
your design won't work in silicon.
Use reset Flip-Flops for the configuration signals of your design. This will ensure that your design goes into a known-state after system reset and will most likely save you lots debugging time in the gate level simulation.
i had looked through the xilinx fpga Libraries Guide
document files,and i find that there are mainly 3 kind of primitives for ffs in xilinx fpga library as following:
ff with asynchronous reset,ff with synchronous reset,
ff without reset.
why the third kind of ff exists?
cause some time we need ff without reset.
in fact,not all of the ffs need to goes into an known state value after power up.
The answer is different for synchronous and asynchronous reset methodologies:
1. Synchronous: you save a gate delay so in case you are looking for ultra high speed this is an option. Often times high speed pipelines only implement reset on the first set of flops and rely on the reset to 'flush' through the pipeline over several clock cycles.
2. Asynchronous: async. reset flops are bigger than those without reset due to the extra transistors needed to force the flop state. Not having resets in places that you can do without it saves you area and leakage power.
In general, I would only trust fairly senior engineers to judge whether to reset a particular flop or no; for new and intermediate designers - enforce everything is reset rule since mistakes come easy when you play with reset.
OK, I'll put my $0.02 in: If there is no reason to leave out the reset for one or more flops, leave it in there. It's better for both simulation and test.
But that said, there are a legitimate reasons for not putting them in. Flops without resets are smaller, faster, and take less power. As long as you know that after a few clocks, the circuit will resolve itself, who needs the reset? Many times, especially in datapath situations, you can initialize a whole path by providing either stimulus or a reset at the beginning of the path, clocking the circuit a number of times, and the rest of the path has known values.
However, be careful, because, you would never want to hope for the same when design a state-machine. FSM's must always power up in a known state.
It depends upon the situation. But err on the side of putting resets in, unless other constraints dictate otherwise.
However, be careful, because, you would never want to hope for the same when design a state-machine. FSM's must always power up in a known state. DFT Digest
I am totally agree with you, for FSM design care should be taken, while designing sequential part of FSM, but while designing output logic of FSM there is no need ot use reset because on power up/reset action, FSM will be in Known (IDLE) stae and output logic is determind on basis of sate of FSM, so if state is known then output will also know at power up.
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