Re: process in vhdl
To Scanman
thank you for your help,
now i have made these two codes which are giving my desire results,
in "12bit_without_rst_modulus.doc" file i have change the RDR output,
in "12bit_without_rst_modulus.doc" where the RDR output is unchanged
dose not giving the proper result when i change the NUM zero to a positive value,
when the NUM is zero then RDR is also zero,but when i just change the zero value of NUM to a positive value in gives RDR=RDR+DEN,
say i give NUM=0, DEN=5, then RDR=0,
but when change the NUM as ,NUM=34(say),then RDR=4+5=9;
so i change the RDR output in my way in "12bit_without_rst_modulus.doc" file