can we initailise an array in verilog

[cccvamshikr]

can we intialise the array in verilog. I mean

input in1;
input in2;
wire w1[1:0] = {in1,in2}

is this a valid syntax.
Thanks in advance...

 

[FvM]

Initializing implies constant expressions, not input signals. If the inputs are connected to a constant in your design hierarchy, it may possibly work.

 

[cccvamshikr]

Thanks for the answer...But how can we use arrays in the design.......if i want to delcare an array as an output how can i declare that..
example: output [15:0]w1 [1:0];
wire w1[1:0];
is this a valid syntax.

 

[FvM]

Standard Verilog doesn't allow structurized signals, e.g. arrays or records, for interfaces. You have to convert them to one dimensional bit vectors for in-and output.

 

[cccvamshikr]

Thank you..thanks alot for the answer...iam parsing the verilog code...thatswhy iam facing these type of problems...