Can we generate a clock(say 1MHz) in FPGA without any input clock

[VLSI_CHE]

i want to know whether we can generate a clock of any specified frequency using VHDL in FPGA without any external clock input to the FPGA. if it is possible to do so, plz tell me the way we can geerate it.

 

[Alexium]

I believe it's not possible to generate stable frequency without external clock. The only inner oscillation source is Johnson–Nyquist noise.

 

[TrickyDicky]

Short answer : No

 

[lucbra]

Some FPGA's of Lattice have an onboard oscillator that you can approach and use in your design. However, these are not the 50ppm stable types. I once did an exercise to use the I/O and some gates in a MachXO to build an oscillator. The I/O was then programmed in Schmitt-Trigger mode. However, this feature has been disabled in later versions of the software.

 

[shanmugaveld]

By connecting odd number of inverters you can generate clcok, but am not sure about its stability.
You can check the frequency through oscilloscope, and you can add more inverters to get the dfferent freq.

 

[TrickyDicky]

By connecting odd number of inverters you can generate clcok, but am not sure about its stability.
You can check the frequency through oscilloscope, and you can add more inverters to get the dfferent freq.

This will just be driven from random noise though. And wont be reliable or give you any specified frequency. it will also be highly affected by temperature.

 

[FvM]

Many FPGA have internal oscillators to load configuration memory in active mode, but don't expose a clock output to the logic fabric. These oscillators are usually ring oscillators (inverter chain, as discussed), mostly with a frequency divider. If you look at the specification, you get a typical 1:2 frequency variation over PVT (process, voltage temperature). Similar numbers can be expected for a "homemade" ring oscillator. It may be still suitable for some applications.

 

[VLSI_CHE]

so can i conclude that we cannot generate a clock without any external clock input to the FPGA?

 

[TrickyDicky]

Thats the basic answer.

 

[mrflibble]

so can i conclude that we cannot generate a clock without any external clock input to the FPGA?

If you want 0 external components, then the only candidate (that I know of) is a ring oscillator. As has been pointed out, for configuration there is also an embedded oscillator, which in turn looks suspiciously much like a ring oscillator. This config oscillator may or may not be available for generic use. My experience with that is, it's not really practically available.

So do your own ring oscillator. Add a counter to do division to get ~ 1 MHz. And don't expect any decent clock. It will have a fair amount of jitter, and will depend on temperature, voltage etc etc. Also be aware that ring oscillators are not low power devices. It can be done, but if it makes sense or not would depend on the application.

For the most part I would say don't do it, unless you really know why you want an internal ring oscillator.

If you are just being cheap, then you add a few external RC components and run your oscillator with that. Again, not great quality, but it's cheap. And again it depends on what you want...

I use ring oscillators in a certain project. But that is only because I want to start the ring oscillator with a trigger signal. Kind of a triggered PLL, but on the cheap. And as such a lot lower quality than a proper PLL setup, but good enough for it's particular use.

And in that project with the ring oscillators I ALSO have a good clock source that is used as the main system clock. The ring oscillators are only used for creative asynchronous logic and fpga abuse in general. In no way am I using it for the main "proper" design. So again, for the most part ... don't do it. If you need a clock source for your general design just get a proper clock source from outside the fpga.

 

[kretzd]

I used to use xilinx devices now it's my first time I write on Lattice. So I have a question to you. How force lattice to implement ring oscillator? In xilinx I have no problem with it but in lattice I can't. Are there any properties i can force that software don't delete my ring oscillator consist of inverters? I write in verilog.

 

[lucbra]

Usually this is done with attributes. I'm used to write VHDL, and I place an attribute 'keep' on the internal net of the ring oscillator.

 

[FvM]

Synthesis attributes are also working with Altera Quartus. But they are tool specific, you have to check the respective manuals, either Synplify or Precision with Lattice.

wire my_wire /* synthesis keep = 1 */; // Verilog	
(* keep = 1 *) wire my_wire; // Verilog-2001

-- VHDL
signal my_wire: bit;
attribute syn_keep: boolean;
attribute syn_keep of my_wire: signal is true;