Junior Member level 1
i want to know whether we can generate a clock of any specified frequency using VHDL in FPGA without any external clock input to the FPGA. if it is possible to do so, plz tell me the way we can geerate it.
By connecting odd number of inverters you can generate clcok, but am not sure about its stability.
You can check the frequency through oscilloscope, and you can add more inverters to get the dfferent freq.
so can i conclude that we cannot generate a clock without any external clock input to the FPGA?
wire my_wire /* synthesis keep = 1 */; // Verilog (* keep = 1 *) wire my_wire; // Verilog-2001 -- VHDL signal my_wire: bit; attribute syn_keep: boolean; attribute syn_keep of my_wire: signal is true;