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Yes its possible to check the setup and hold time after synthesis(for ur netlist) but u have to have the simulation model for ur .lib which u used for synthesis.
Functional simulation with behavioural code we can't check setup and hold times .
setup & hold times of a FLOP is coming only if you have Flops with delay checks and wires annotated with delay .
Thanks & Regards
yln
We cant check the Set up and hold time in functional simulation but u can check it after the synthesis if ur .lib file have the info of the technology timing constraints.
we can check the setup and hold violation by using RTL code, if u have netlist by using tools loke ex:nc verilog we can find the setup and hold violations
We can check the setup and hold time analysis after the synthesis but it is better to do the setup and hold time analysis after P&R. because the lack of clock tree the clock will not propagate correctly.so the timing analysis after synthesis before P&R it not advisble.
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