can we change the internal memory(DDR2)? is there a crystal clock inside?

[hfss_newbie]

can we change the internal memory(DDR2) clock? is there a crystal clock inside?

Hello guys,

Here is my question. i have bought a DDR2 memory and when i look at the datasheet, it doesn't talk about the internal clock freq. of DDR2.
Does it mean that there is no crystal clock inside? if not is the working freq. supplied by DDR2 controller? or by clock tree which is completely independant of DDR2 controller?

when i buy a DDR2, is the speed grade fixed or we can program it?
in order to see where my confusion comes from, below is the table of speed grade in datasheet of Micron DDR2 that i've bought. it shows different speed grades, and i believe it means that i can program my DDR2 internal clock to have these speed grades on I/O bus which comes out of DDR2.

Key Timing Parameters(Data Rates(MT/s)

Speed Grade CL = 3 CL = 4 CL = 5 CL = 6 CL = 7
-187E 400 533 800 800 1066
-25E 400 533 800 800 n/a
-25 400 533 667 800 n/a
-3 400 533 667 n/a n/a

Is that true?
thanks for any comment

 

[mrflibble]

I suggest reading this one: https://en.wikipedia.org/wiki/DDR_SDRAM

 

[FvM]

You don't program the clock. You'll apply an external clock (named "bus clock" in the Wikipedia article) of half the data rate and specify latency with a command during memory initialization. As you see from the table, faster speed grades are always downwards compatible.

The DDRx RAMs have an internal PLL locking to the external clock that generates the internal timing. Due to this PLL, the operation frequency has a lower limit.

 

[syedshan]

sorry to interrupt in the middle, but I also got confused couple of days back...

1. The half data rate clock is given input to the DDR3 where as we should also
2. We should also give the DQS/DQS# differential clock as well along with our data, right? (like generate from FPGA )

All in all we should have 2 clocks going input to the DDR3?

- - - Updated - - -

sorry to interrupt in the middle, but I also got confused couple of days back...

1. The half data rate clock is given input to the DDR3 where as we should also
2. We should also give the DQS/DQS# differential clock as well along with our data, right? (like generate from FPGA )

All in all we should have 2 clocks going input to the DDR3?

 

[FvM]

DQS is called "data strobe". It's a bidirectional signal, used with all DDRx variants. It's not independent of main clock CK. With DDR3, the new "write leveling" feature has been introduced, allowing a larger skew of DQS relative to CK.