xuguang
Newbie level 2

I am not clear enough to below job.
Can anyone help me understand it?
1 is this job same as CAD?
2 does it have good future?
Thanks in advance.
Xuguang
SR. PHYSICAL DESIGN METHODOLOGY ENGINEER
RESPONSIBILITIES:
- Responsible for the development of the physical design methodologies and flow automation for large and high speed semicustom chips using deep submicron processes.
- This includes evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the physical design implementation team.
MINIMUM REQUIREMENTS:
- BSEE or BSCS
- 5+ years of experience in large VLSI physical design implementation and automation and methodology.
- Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, xtalk analysis, signal EM, place and route, DRC/LVS and tapeout issues.
- Working knowledge of deep sub-micron issues.
- Should be a power user of P&R and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (ICC/DC/PT/STAR-RC/Astro/PC), Cadence (SOCE), Mentor Graphics (Pinnacle/Olympus) or Atoptech.
- Proficiency using Perl, TCL, Make scripting.
- Knowledge / Proficiency of C / C++ or any other software language is a plus.
- Experience at 40nm and 28nm is a plus.
- Circuit level comprehension of time critical paths and Spice experience are a plus.
Can anyone help me understand it?
1 is this job same as CAD?
2 does it have good future?
Thanks in advance.
Xuguang
SR. PHYSICAL DESIGN METHODOLOGY ENGINEER
RESPONSIBILITIES:
- Responsible for the development of the physical design methodologies and flow automation for large and high speed semicustom chips using deep submicron processes.
- This includes evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the physical design implementation team.
MINIMUM REQUIREMENTS:
- BSEE or BSCS
- 5+ years of experience in large VLSI physical design implementation and automation and methodology.
- Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, xtalk analysis, signal EM, place and route, DRC/LVS and tapeout issues.
- Working knowledge of deep sub-micron issues.
- Should be a power user of P&R and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (ICC/DC/PT/STAR-RC/Astro/PC), Cadence (SOCE), Mentor Graphics (Pinnacle/Olympus) or Atoptech.
- Proficiency using Perl, TCL, Make scripting.
- Knowledge / Proficiency of C / C++ or any other software language is a plus.
- Experience at 40nm and 28nm is a plus.
- Circuit level comprehension of time critical paths and Spice experience are a plus.