Can SCMOS DRC rule 11.6 be waived?

[zenphyx]

Hi,

Can I safely ignore the following DRC errors? Has anyone tried waiving these errors before with MOSIS?

(SCMOS Rule 11.6) poly2 to unrelated metal2 spacing: 0.60 um
(SCMOS Rule 11.6) poly2 to unrelated metal3 spacing: 0.60 um

I am working on a VLSI electrode array in which real-estate is critical. I cannot afford to route around a poly-poly2 capacitor as it significantly increases the area per each electrode cell. I don't really care about the parasitic capacitance the routing adds. I appreciate any help on the matter.

Thx!

 

[erikl]

I think there's no physical reason why you couldn't (or shouldn't) do this - as long as you don't fear any interaction between these nodes - impact on both nodes considered. If matching matters, over-routing has to be symmetrical, of course.

Waiving these DRC errors with MOSIS is another matter. Try and explain it thoroughly, with snap shots and coordinates.