Can I use this Verilog style inside VHDL ?

[omara007]

Hi guys ..

Is it allowed to use the verilog style of representing values like :
x = 32'b0

in VHDL ?

 

[Guru59]

No you have to use as

x = "0000000000000000000000000000000"

I think...............correct me if i am wrong

 

[omara007]

No you have to use as

x = "0000000000000000000000000000000"

I think...............correct me if i am wrong

This is the normal way .. but sometimes u may have very large buses and it's not easy to assign the values to them this way ..

I once saw some vhdl code like this :

x = 16#0#

Anyone tried that style before ? .. I tried it with 32#0# but it didn't work !! dunno what was the problem !!!

 

[khaila]

sure not.
but in VHDL you may use:

x <= (other => '0');

I think it is smartest that Verilog while there is no need to declire the lenght/width!!

 

[aji_vlsi]

sure not.
but in VHDL you may use:

x <= (other => '0');

I think it is smartest that Verilog while there is no need to declire the lenght/width!!

In SystemVerilog you have unsized 'b that takes care of this length/width:


x <= 'b0; // No SIZE specification

HTH
Ajeetha, CVC
www.noveldv.com

Added after 2 minutes:

[
This is the normal way .. but sometimes u may have very large buses and it's not easy to assign the values to them this way ..

There are array aggregates that let you do this nicely in VHDL. Take a look at VHDL FAQ at www.vhdl.org/comp.lang.vhdl

I once saw some vhdl code like this :

x = 16#0#

Anyone tried that style before ? .. I tried it with 32#0# but it didn't work !! dunno what was the problem !!!

I've used it, it works fine. IIRC, this was added in VHDL 93, maybe your tool has a flag for V93 and you didn't turn it on?

Regards
Ajeetha, CVC
www.noveldv.com

 

[omara007]

sure not.
but in VHDL you may use:

x <= (other => '0');

I think it is smartest that Verilog while there is no need to declire the lenght/width!!

this won't work with a value of 23 for example .. it only works if u want to load x with all zeros ..

Added after 1 minutes:

sure not.
but in VHDL you may use:

x <= (other => '0');

I think it is smartest that Verilog while there is no need to declire the lenght/width!!

In SystemVerilog you have unsized 'b that takes care of this length/width:


x <= 'b0; // No SIZE specification

HTH
Ajeetha, CVC
www.noveldv.com

Added after 2 minutes:

[
This is the normal way .. but sometimes u may have very large buses and it's not easy to assign the values to them this way ..

There are array aggregates that let you do this nicely in VHDL. Take a look at VHDL FAQ at www.vhdl.org/comp.lang.vhdl

I once saw some vhdl code like this :

x = 16#0#

Anyone tried that style before ? .. I tried it with 32#0# but it didn't work !! dunno what was the problem !!!

I've used it, it works fine. IIRC, this was added in VHDL 93, maybe your tool has a flag for V93 and you didn't turn it on?

Regards
Ajeetha, CVC
www.noveldv.com

Does 32#0# mean 32 zeros or a zero based on a 32 digits numbering system ? .. (for sure there is no 32 base for a numbering system) ..

I have indeed switched on the VHDL 93 compliant compilation .. (-v93 in Cadence NC)... but still I'm getting this error :

based literal base out of bounds [13.4.2].

 

[er.akhilkumar]

You can use b <= (others => '0'); if you want to assign zero to full width of vector. But if you want to write a specific value then you can write it in hexadecimal and binary format.

for writing in binary format you can use b <= "01010101"; and b <= 2#01010101#.

for writing in hexadecimal format you can use b <= x"55"; and b <= 16#55#;

For writing in any other numbering system you can use b <= numbering_system#value#;

 

[hbeck]

readable version to assign integer values to ulogic vectors:

b <= std_ulogic_vector(to_unsigned(10, b'length));