Can I use rising and falling edge in one design for clock?

[ftian]

One question about clock

Can I use both rising edge and falling edge in the same design for one clock?


Thanks,
Jay

 

[tutx]

One question about clock

Of cours, U can you both of them in the same design for one clock. However, pay attention when using two clock in a functional block. It maybe gets you into trouble !

Brds,

 

[ftian]

One question about clock

Thanks tutx, Is there anything need to be taken care of when using both edge of one clock?

any documents talk about this?

 

[papyaki]

Re: One question about clock

Hi,

You can use such clocking scheme when you want to sample an input and process it in the same clock period. You can, for example, latch your input's state on raising edge and process the latched value on the falling edge of the same clock period.

This is possible without trouble with one clock. If you are using two clocks (named also two domains), the best way is to use FIFOs. Datas are latched into the FIFO on one edge of the first clock and are processed out of the FIFO on one edge of the second clock.

 

[ftian]

One question about clock

Assuming I use both clock edges in the design, any problems during STA?

How does STA tools know which clock edge I am using? accroding to the flip-flop used?

 

[gaonkc]

One question about clock

Normally use posedge for clk, special case use rise or fall of clk, you can use the the inverter of main clock to trigger

 

[tom123]

Re: One question about clock

you'd better not to do so.

because if you use both rising edge and failing edge of a clock,

then the clock's duty cycle must be take into account.

that's hard to deal with.

Can I use both rising edge and falling edge in the same design for one clock?


Thanks,
Jay

 

[Karthikeya]

Re: One question about clock

tom123
the clock's duty cycle is normally 50% right...then how is it hard to deal???the rise edge and fall edge occur at period intervals

 

[YUV]

Re: One question about clock

Using of both clock edges may cause a lack of setup/hold time at high frequencies. You should be careful.

 

[tutx]

One question about clock

You can use both of two edges of clock for your design but you should not use more than one clock in a function block.

 

[dolby.yang]

Re: One question about clock

you can use one clk's pos edge and neg edge both in one design ,but i think it will be more safe to use 2 multiple clk with you source clk singnal .

 

[barkha]

Re: One question about clock

For increase data throughput rates, use is
sometimes made of both the rising and the falling clock
edge for clocked elements. But it causes a number of
problems, in particular:
• An asymmetrical clock duty cycle can cause setup and
hold violations.
• It is difficult to determine critical signal paths.
• Test methodologies such as scan-path insertion are
difficult, as they rely on all flip-flops being activated on
the same clock edge. If scan insertion is required in a
circuit with double-edged clocking, multiplexers must be
inserted in the clock lines to change to single-edged
clocking in test mode.
It will be more safe to use 2 multiple clk with you source clk singnal .

 

[quake]

Re: One question about clock

For increase data throughput rates, use is
sometimes made of both the rising and the falling clock
edge for clocked elements. But it causes a number of
problems, in particular:
• An asymmetrical clock duty cycle can cause setup and
hold violations.
• It is difficult to determine critical signal paths.
• Test methodologies such as scan-path insertion are
difficult, as they rely on all flip-flops being activated on
the same clock edge. If scan insertion is required in a
circuit with double-edged clocking, multiplexers must be
inserted in the clock lines to change to single-edged
clocking in test mode.
It will be more safe to use 2 multiple clk with you source clk singnal .

HI. The problem is when both pose and neg edges are used in the same block, how
do you do the STA of it? any special methodology? Is this comdition the same as we design two phase clock latch based module?
and how do you sovle the above three problems and gurrenty you design is OK to sign off?
thanks

 

[bg21359]

Re: One question about clock

You should have extra clock skew for duty cycle variation. So for STA, you just need to add more clock skew if the time path includes both clk edges.

 

[ravindra kalla]

Re: One question about clock

hi,

i think it will not be a good design.

it will creat problem on setup and hold time.and u should be more concentrate about delay on ur component on your design.

ok

 

[rakko]

Re: One question about clock

Seems like everyone listed here why not use both edges and they all are right. If you need to do more tasks in a clock cycle, shift your clock and use the new shifted rising edge in place of falling edge to do your tasks. Microprocessors use this technique in their pipeline.

 

[stocking]

One question about clock

of course! but it is not best chance since there are some troubles doing scan insertion ! you had better use single edge if you can so!

 

[funster]

Re: One question about clock

you'd better not to do this, because this will

put duty cycle restriction on your clock.

you can use double frequency clock to realize your intent.


best regards

Can I use both rising edge and falling edge in the same design for one clock?


Thanks,
Jay

 

[jackson_peng]

One question about clock

it not recomended.
because it's hard to have a 50% duty cycle PLL and the it's more complicated for CTS to consider both duty cycle, rise and fall transition time.

 

[jjww110]

One question about clock

of course,you can , but you must take care on timing