Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Can I use rising and falling edge in one design for clock?

Status
Not open for further replies.

ftian

Newbie level 5
Newbie level 5
Joined
Oct 13, 2004
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
95
One question about clock

Can I use both rising edge and falling edge in the same design for one clock?


Thanks,
Jay
 

tutx

Full Member level 2
Full Member level 2
Joined
Mar 4, 2004
Messages
121
Helped
13
Reputation
26
Reaction score
1
Trophy points
1,298
Activity points
884
One question about clock

Of cours, U can you both of them in the same design for one clock. However, pay attention when using two clock in a functional block. It maybe gets you into trouble !

Brds,
 

ftian

Newbie level 5
Newbie level 5
Joined
Oct 13, 2004
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
95
One question about clock

Thanks tutx, Is there anything need to be taken care of when using both edge of one clock?

any documents talk about this?
 

papyaki

Advanced Member level 2
Advanced Member level 2
Joined
Apr 13, 2002
Messages
538
Helped
38
Reputation
76
Reaction score
19
Trophy points
1,298
Location
France
Activity points
5,346
Re: One question about clock

Hi,

You can use such clocking scheme when you want to sample an input and process it in the same clock period. You can, for example, latch your input's state on raising edge and process the latched value on the falling edge of the same clock period.

This is possible without trouble with one clock. If you are using two clocks (named also two domains), the best way is to use FIFOs. Datas are latched into the FIFO on one edge of the first clock and are processed out of the FIFO on one edge of the second clock.
 

ftian

Newbie level 5
Newbie level 5
Joined
Oct 13, 2004
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
95
One question about clock

Assuming I use both clock edges in the design, any problems during STA?

How does STA tools know which clock edge I am using? accroding to the flip-flop used?
 

gaonkc

Advanced Member level 4
Full Member level 1
Joined
Jul 16, 2004
Messages
103
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
635
One question about clock

Normally use posedge for clk, special case use rise or fall of clk, you can use the the inverter of main clock to trigger
 

tom123

Advanced Member level 4
Full Member level 1
Joined
Apr 4, 2005
Messages
116
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Activity points
2,338
Re: One question about clock

you'd better not to do so.

because if you use both rising edge and failing edge of a clock,

then the clock's duty cycle must be take into account.

that's hard to deal with.



ftian said:
Can I use both rising edge and falling edge in the same design for one clock?


Thanks,
Jay
 

Karthikeya

Advanced Member level 4
Full Member level 1
Joined
Jan 9, 2005
Messages
103
Helped
9
Reputation
18
Reaction score
1
Trophy points
1,298
Activity points
987
Re: One question about clock

tom123
the clock's duty cycle is normally 50% right...then how is it hard to deal???the rise edge and fall edge occur at period intervals
 

YUV

Advanced Member level 4
Full Member level 1
Joined
Sep 26, 2002
Messages
114
Helped
12
Reputation
24
Reaction score
3
Trophy points
1,298
Location
Ukraine
Activity points
1,191
Re: One question about clock

Using of both clock edges may cause a lack of setup/hold time at high frequencies. You should be careful.
 

tutx

Full Member level 2
Full Member level 2
Joined
Mar 4, 2004
Messages
121
Helped
13
Reputation
26
Reaction score
1
Trophy points
1,298
Activity points
884
One question about clock

You can use both of two edges of clock for your design but you should not use more than one clock in a function block.
 

dolby.yang

Member level 4
Member level 4
Joined
Mar 2, 2005
Messages
73
Helped
10
Reputation
20
Reaction score
2
Trophy points
1,288
Activity points
1,862
Re: One question about clock

you can use one clk's pos edge and neg edge both in one design ,but i think it will be more safe to use 2 multiple clk with you source clk singnal .
 

barkha

Advanced Member level 4
Full Member level 1
Joined
Aug 8, 2005
Messages
114
Helped
21
Reputation
42
Reaction score
10
Trophy points
1,298
Location
India
Activity points
2,576
Re: One question about clock

For increase data throughput rates, use is
sometimes made of both the rising and the falling clock
edge for clocked elements. But it causes a number of
problems, in particular:
• An asymmetrical clock duty cycle can cause setup and
hold violations.
• It is difficult to determine critical signal paths.
• Test methodologies such as scan-path insertion are
difficult, as they rely on all flip-flops being activated on
the same clock edge. If scan insertion is required in a
circuit with double-edged clocking, multiplexers must be
inserted in the clock lines to change to single-edged
clocking in test mode.
It will be more safe to use 2 multiple clk with you source clk singnal .
 

quake

Member level 5
Member level 5
Joined
Nov 23, 2004
Messages
86
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,286
Activity points
882
Re: One question about clock

barkha said:
For increase data throughput rates, use is
sometimes made of both the rising and the falling clock
edge for clocked elements. But it causes a number of
problems, in particular:
• An asymmetrical clock duty cycle can cause setup and
hold violations.
• It is difficult to determine critical signal paths.
• Test methodologies such as scan-path insertion are
difficult, as they rely on all flip-flops being activated on
the same clock edge. If scan insertion is required in a
circuit with double-edged clocking, multiplexers must be
inserted in the clock lines to change to single-edged
clocking in test mode.
It will be more safe to use 2 multiple clk with you source clk singnal .

HI. The problem is when both pose and neg edges are used in the same block, how
do you do the STA of it? any special methodology? Is this comdition the same as we design two phase clock latch based module?
and how do you sovle the above three problems and gurrenty you design is OK to sign off?
thanks
 

bg21359

Member level 3
Member level 3
Joined
Mar 1, 2005
Messages
56
Helped
7
Reputation
12
Reaction score
5
Trophy points
1,288
Activity points
1,802
Re: One question about clock

You should have extra clock skew for duty cycle variation. So for STA, you just need to add more clock skew if the time path includes both clk edges.
 

ravindra kalla

Junior Member level 2
Junior Member level 2
Joined
Aug 3, 2005
Messages
24
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,519
Re: One question about clock

hi,

i think it will not be a good design.

it will creat problem on setup and hold time.and u should be more concentrate about delay on ur component on your design.

ok
 

rakko

Full Member level 4
Full Member level 4
Joined
Jun 1, 2001
Messages
233
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,298
Location
mozambic
Activity points
2,065
Re: One question about clock

Seems like everyone listed here why not use both edges and they all are right. If you need to do more tasks in a clock cycle, shift your clock and use the new shifted rising edge in place of falling edge to do your tasks. Microprocessors use this technique in their pipeline.
 

stocking

Member level 5
Member level 5
Joined
Nov 5, 2004
Messages
91
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,288
Activity points
704
One question about clock

of course! but it is not best chance since there are some troubles doing scan insertion ! you had better use single edge if you can so!
 

funster

Full Member level 4
Full Member level 4
Joined
Jun 30, 2005
Messages
232
Helped
19
Reputation
38
Reaction score
4
Trophy points
1,298
Activity points
2,742
Re: One question about clock

you'd better not to do this, because this will

put duty cycle restriction on your clock.

you can use double frequency clock to realize your intent.


best regards





ftian said:
Can I use both rising edge and falling edge in the same design for one clock?


Thanks,
Jay
 

jackson_peng

Full Member level 2
Full Member level 2
Joined
Apr 11, 2005
Messages
139
Helped
24
Reputation
48
Reaction score
9
Trophy points
1,298
Location
Shanghai, China
Activity points
2,380
One question about clock

it not recomended.
because it's hard to have a 50% duty cycle PLL and the it's more complicated for CTS to consider both duty cycle, rise and fall transition time.
 

jjww110

Full Member level 5
Full Member level 5
Joined
Apr 19, 2005
Messages
255
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
china
Activity points
2,920
One question about clock

of course,you can , but you must take care on timing
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top