Can I use array in VHDL

[xilinx1001]

Hi,

I need to use array to store 6 bytes in vhdl?

what is the syntax for array in VHDL?

How can I store 6 bytes?

How can I call individual byte?


Thanks in advance
xilinx1001

 

[aria62]

hi,
you can first specify a new array type using this syntax:

TYPE type_name IS ARRAY (specification) OF data_type;

then you can make use of the new array by this code:

SIGNAL signal_name: type_name [:= initial_value];

EXAMPLE for saving 6 bytes:===============================

TYPE matrix IS ARRAY (0 TO 5) OF STD_LOGIC_VECTOR(7 DOWNTO 0); --type definitions
SIGNAL x: matrix; --signal declarations
matrix <= ("00010101","11111111","10101010","00000000","11001100","11100010"); --an example of signal assignment


Hope this helps;

 

[xilinx1001]

Hi,

I need to give two 9 bit values(cm, cm2) to an array

cm and cm2 contains the two 9 bit values

I am doing something like this

TYPE matrix IS ARRAY (0 TO 2) OF STD_LOGIC_VECTOR(8 DOWNTO 0); --type definitions
SIGNAL x: matrix; --signal declarations

matrix(0)<= cm,
matrix(1)<=cm2

Can you suggest anything about this?


Regards
xilinx1001

 

[aria62]

hi,

first of all if your array has two rows, correct your range:
TYPE matrix IS ARRAY (0 TO 1) OF STD_LOGIC_VECTOR (8 DOWNTO 0);

the other point is cm and cm2 have to be of type std_logic_vector(8 DOWNTO 0)

good luck,