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[SOLVED] Can I use a Virtual clock instead of using a create_clock?

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coshy

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Hi,

I'm confusing that whether virtual clock declaration can use instead of real clock's create_clock.
Because I came across the SDC file what there is no definition of create_clock for real clock.

Basically, We use Clock Definition as the below.
###################################
#
# CLOCK DEFINITION
#
###################################

# A 333Mhz clock is a 3.0ns period:
#
create_clock -period 3.0 [get_ports clk]

But I found a different declaration of definition clock.
###################################
# #
# CLOCK DEFINITION #
# #
###################################

# A 333Mhz clock is a 3.0ns period:
#
create_clock -period 3.0 -name my_clk -waveform {0 1.2} [get_ports clk]
As you can see this is a definition of virtual clock it's not similar with definition from above it.



Here is definition of a virtual clock.
What is a virtual clock: By definition, a virtual clock is a clock without any source. Stating more clearly, a virtual clock is a clock that has been defined, but has not been associated with any pin/port. A virtual clock is used as a reference to constrain the interface pins by relating the arrivals at input/output ports with respect to it with the help of input and output delays.


Can I use a Virtual clock instead of using a create_clock? Or Should I have to use a Virtial Clock Only for non clock source system.?
 

FvM

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# A 333Mhz clock is a 3.0ns period:
#
create_clock -period 3.0 -name my_clk -waveform {0 1.2} [get_ports clk]
As you can see this is a definition of virtual clock it's not similar with definition from above it.

There's nothing related to virtual clock in your second create_clock example, the only relevant difference is the -waveform specification definining an asymetrical duty cycle. Particularly it has a source, thus can't be virtual. Did you quote the wrong sdc statement?
--- Updated ---

Virtual clocks are e.g. used to constrain the timing of I/O signals, see example from Quartus SDC manual
# create a virtual clock
create_clock -name virtual -period 1
# apply input/output delays with the virtual clock to get
# I/O interface uncertainties
set_input_delay -clock virtual -add_delay 0 [all_inputs]
set_output_delay -clock virtual -add_delay 0 [all_outputs]
 
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coshy

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There's nothing related to virtual clock in your second create_clock example, the only relevant difference is the -waveform specification definining an asymetrical duty cycle. Particularly it has a source, thus can't be virtual. Did you quote the wrong sdc statement?
--- Updated ---

Virtual clocks are e.g. used to constrain the timing of I/O signals, see example from Quartus SDC manual

Let me check it with your answer. But, the usage of definition virtual clock. As Far I Know, If I declare the clock with "-name" then it should work as virtual clock. So I was asking with it.
I refered with https://electronics.stackexchange.c...gister-to-register-and-input-to-output-in-sta

I'm trying to get a report of timing path from input to output.
AS you can see the my previous post,
I used as the below SDC.


Code:
report_timing -from [all_inputs]               -to [all_registers -data_pins] -max_paths 10 > report_input2r.rpt
report_timing -from [all_registers -data_pins] -to [all_registers -data_pins] -max_paths 10 > report_reg2r.rpt
report_timing -from [all_registers -data_pins] -to [all_outputs]              -max_paths 10 > report_reg2o.rpt
report_timing -from [all_inputs]               -to [all_outputs]              -max_paths 10 > report_intput2out.rpt

then I got some report.
But that report doesn't use a virtual clock definition. so I think that the input Cin1[4:0] and Cin2[4:0] and output Cout[4:0] must be wrong.

So I asked that I need to define the virtual clock for get a right report.
and one thing issue is that why I can't get the register to output report?


And I've got the report report_reg2output but it seems something wrong.
Why can't report with any path? Did I something to do wrong?

Code:
****************************************
Report : timing
-path full
-delay max
-max_paths 10
Design : MY_DESIGN
****************************************

Wire Load Model Mode: enclosed
No paths.

1

If I wrong to get the reports from all 4 paths, Could you guide me how can I get correct reports from it?
 
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FvM

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As Far I Know, If I declare the clock with "-name" then it should work as virtual clock.

-name has nothing to do with virtual clock specification. Synopsys Timing Constraints and Optimization User Guide clarifies:
You can optionally specify a name for the clock with the -name option. If you do not specify a name explicitly, the clock gets its name from the source object.

As you state correctly in post #1:
By definition, a virtual clock is a clock without any source. Stating more clearly, a virtual clock is a clock that has been defined, but has not been associated with any pin/port.
 
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